reg.vhd

来自「for FPGA IMPLEMENTATION,OUR DATAPATH CRE」· VHDL 代码 · 共 34 行

-- ============================================================
-- File Name: register.vhd
-- ============================================================

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY reg IS 
	PORT
	(
		clk		: IN STD_LOGIC;
		ld		: IN STD_LOGIC;
		din		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		dout	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END reg;

ARCHITECTURE behavior OF reg IS

BEGIN

	PROCESS (clk)
	BEGIN
		IF (clk'EVENT AND clk = '1') THEN
			IF (ld = '1') THEN 
				dout <= din;
			END IF;
		END IF;
	END PROCESS;

END behavior;