alu.vhd

for FPGA IMPLEMENTATION,OUR DATAPATH CREATED FOR TWO BIRS MULTIPLICATION

-- ============================================================
-- File Name: alu.vhd
-- ============================================================

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY alu IS 
	PORT
	(
		clk		: IN STD_LOGIC;
		ld_x	: IN STD_LOGIC;
		ld_y	: IN STD_LOGIC;
		aludr	: IN STD_LOGIC;
		funct	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		din		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		dout	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END alu;

ARCHITECTURE structure OF alu IS

COMPONENT reg
	PORT
	(
		clk		: IN STD_LOGIC;
		ld		: IN STD_LOGIC;
		din		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		dout	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END COMPONENT;

COMPONENT math_logic
	PORT
	(
		aludr	: IN STD_LOGIC;
		funct	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		xdin	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		ydin	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		dout	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END COMPONENT;

SIGNAL r_xreg, r_yreg	: STD_LOGIC_VECTOR (7 DOWNTO 0);

BEGIN

	r_xreg <= "ZZZZZZZZ";
	r_yreg <= "ZZZZZZZZ";

	U0 : reg PORT MAP(clk, ld_x, din, r_xreg);
	U1 : reg PORT MAP(clk, ld_y, din, r_yreg);
	U2 : math_logic PORT MAP(aludr, funct, r_xreg, r_yreg, dout);

END structure;