seg.vhd

这是一个用VHDL语言编写的数字电路程序

library ieee;
use ieee.std_logic_1164.all;

entity seg is
port(
     clk400h:in std_logic;
     sec_one:in std_logic_vector(3 downto 0);
     sec_ten:in std_logic_vector(3 downto 0);
     min_one:in std_logic_vector(3 downto 0);
     min_ten:in std_logic_vector(3 downto 0);
     hour_one:in std_logic_vector(3 downto 0);
     hour_ten:in std_logic_vector(3 downto 0);
     cat:out std_logic_vector(5 downto 0);
     mux_o:out std_logic_vector(6 downto 0)
);
end seg;

architecture seg_c of seg is
signal q:integer range 0 to 5;
signal mux_out:std_logic_vector(3 downto 0);  --数码管输出数组    
begin
 process(clk400h)
  begin
    if(clk400h'event and clk400h='1') then
       if q=5 then q<=0;
       else q<=q+1; 
       end if;
    end if; 
    case q is
    when 0 =>mux_out<= sec_one; cat<="111110";
    when 1 =>mux_out<= sec_ten; cat<="111101";
    when 2 =>mux_out<= min_one; cat<="111011";
    when 3 =>mux_out<= min_ten; cat<="110111";
    when 4 =>mux_out<= hour_one; cat<="101111";
    when 5 =>mux_out<= hour_ten; cat<="011111";
    end case;
   case mux_out is              --实现４位向量与７段数码管输出之间的转换
   when "0000"=>mux_o<="1111110";
   when "0001"=>mux_o<="0110000";
   when "0010"=>mux_o<="1101101";
   when "0011"=>mux_o<="1111001";
   when "0100"=>mux_o<="0110011";
   when "0101"=>mux_o<="1011011";
   when "0110"=>mux_o<="1011111";
   when "0111"=>mux_o<="1110000";
   when "1000"=>mux_o<="1111111";
   when "1001"=>mux_o<="1111011";
   when others=>mux_o<="0000000";
   end case; 
 end process;
end;