div.vhd

来自「这是一个用VHDL语言编写的数字电路程序」· VHDL 代码 · 共 42 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity div is
port(
     clk:in std_logic;
     clk400h:out std_logic;
     clk1h:out std_logic
);
end div;

architecture div_a of div is
signal q1 : integer range 0 to 1249;
signal q2:integer range 0 to 199;
signal y:std_logic:='0';
signal y1:std_logic:='0';
begin
p1:process(clk)  --将1M的时钟2500分频得到400h的信号
begin
if(clk'event and clk='1') then
  if q1=1249 then
     q1<=0;y<=not y;
  else q1<=q1+1;
  end if;
end if;
end process;

p2:process(y) --将400h的信号400分频得到1h的信号
begin
if(y'event and y='1') then
  if q2=199 then 
      q2<=0;y1<=not y1;
  else  q2<=q2+1;
  end if;
end if;
end process;

clk400h<=y;
clk1h<=y1;

end;