shizhi.vhd

来自「这是一个用VHDL语言编写的数字电路程序」· VHDL 代码 · 共 34 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity shizhi is
port(
     qiehuan:in std_logic;
     hour_one:in std_logic_vector(3 downto 0);
     hour_ten:in std_logic_vector(3 downto 0);
     hour1_one:out std_logic_vector(3 downto 0);
     hour1_ten:out std_logic_vector(3 downto 0);
     a:out std_logic
);
end shizhi;

architecture shizhi_d of shizhi is
begin
 process(qiehuan)
  begin
   if qiehuan='1' then
      if (hour_one>"0001" and hour_ten>"0000") then
          hour1_ten<=hour_ten-1;
          hour1_one<=hour_one-2;
          a<='1';
      else  hour1_one<=hour_one;
            hour1_ten<=hour_ten;
            a<='0';
      end if;
   else hour1_one<=hour_one;
        hour1_ten<=hour_ten;
        a<='0';
   end if;
 end process;
end;