clock.vhd

这是一个用VHDL语言编写的数字电路程序

library ieee;
use ieee.std_logic_1164.all;

entity clock is
port(
     clk,res,change,add_min,add_hour,qiehuan:in std_logic;
     mux_o:out std_logic_vector(6 downto 0);
     cat:out std_logic_vector(5 downto 0);
     a:out std_logic     
);
end clock;

architecture clock_e of clock is
component div
port(
     clk:in std_logic;
     clk400h:out std_logic;
     clk1h:out std_logic
);
end component;
component count
port(
     clk1h:in std_logic;
     change:in std_logic;
     add_min:in std_logic;
     add_hour:in std_logic;
     res:in std_logic;
     sec_one:out std_logic_vector(3 downto 0);
     sec_ten:out std_logic_vector(3 downto 0); 
     min_one:out std_logic_vector(3 downto 0); 
     min_ten:out std_logic_vector(3 downto 0); 
     hour_one:out std_logic_vector(3 downto 0); 
     hour_ten:out std_logic_vector(3 downto 0)  
);
end component;
component seg
port(
     clk400h:in std_logic;
     sec_one:in std_logic_vector(3 downto 0);
     sec_ten:in std_logic_vector(3 downto 0);
     min_one:in std_logic_vector(3 downto 0);
     min_ten:in std_logic_vector(3 downto 0);
     hour_one:in std_logic_vector(3 downto 0);
     hour_ten:in std_logic_vector(3 downto 0);
     cat:out std_logic_vector(5 downto 0);
     mux_o:out std_logic_vector(6 downto 0)
);
end component;
component shizhi
port(
     qiehuan:in std_logic;
     hour_one:in std_logic_vector(3 downto 0);
     hour_ten:in std_logic_vector(3 downto 0);
     hour1_one:out std_logic_vector(3 downto 0);
     hour1_ten:out std_logic_vector(3 downto 0);
     a:out std_logic
);
end component;

signal clk400hz,clk1hz:std_logic;
signal sec_l,sec_h,min_l,min_h,hour_l,hour_h,
       hour1_l,hour1_h:std_logic_vector(3 downto 0);
begin
u1:div port map(clk=>clk,clk400h=>clk400hz,clk1h=>clk1hz);
u2:count port map(clk1h=>clk1hz,res=>res,                  
                  change=>change,
                  add_min=>add_min,
                  add_hour=>add_hour,
                  sec_one=>sec_l,sec_ten=>sec_h,
                  min_one=>min_l,min_ten=>min_h,
                  hour_one=>hour_l,hour_ten=>hour_h);
u3:shizhi port map(qiehuan=>qiehuan,                  
                  hour_one=>hour_l,hour_ten=>hour_h,
                  hour1_one=>hour1_l,hour1_ten=>hour1_h,
                  a=>a);
u4:seg port map  (clk400h=>clk400hz,
                  sec_one=>sec_l,
                  sec_ten=>sec_h,
                  min_one=>min_l,
                  min_ten=>min_h,
                  hour_one=>hour1_l,
                  hour_ten=>hour1_h,
                  mux_o=>mux_o,
                  cat=>cat);
end;