count.vhd

这是一个用VHDL语言编写的数字电路程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity count is
port(
     clk1h:in std_logic;
     change:in std_logic;
     add_min:in std_logic;
     add_hour:in std_logic;
     res:in std_logic;
     sec_one:out std_logic_vector(3 downto 0);
     sec_ten:out std_logic_vector(3 downto 0); 
     min_one:out std_logic_vector(3 downto 0); 
     min_ten:out std_logic_vector(3 downto 0); 
     hour_one:out std_logic_vector(3 downto 0); 
     hour_ten:out std_logic_vector(3 downto 0)  
);
end count;

architecture count_b of count is
signal sec,min:integer range 0 to 59;
signal hour:integer range 0 to 23;
begin
process(clk1h,res,change,add_min,add_hour)
  begin
     if(res='1') then sec<=0;min<=0;hour<=0;
     elsif (clk1h'event and clk1h='1') then 
       if(change='0') then                       
          if sec=59 then
             sec<=0;
             if min=59 then
                min<=0;
                if hour=23 then hour<=0;
                else hour<=hour+1;
                end if;
             else min<=min+1;
             end if;
          else sec<=sec+1;
          end if;  
       else  
           sec<=0;                  
           case add_min is
           when '1'  =>  if min=59 then min<=0;
                         else min<=min+1;
                         end if;
           when others=> null;
           end case;
           case add_hour is
           when '1'  =>  if hour=23 then hour<=0;
                         else hour<=hour+1;
                         end if;
           when others=> null;
           end case;
       end if;
     else null;
     end if; 
 end process;
sec_one<=conv_std_logic_vector(sec mod 10,4);
sec_ten<=conv_std_logic_vector(sec/10,4);
min_one<=conv_std_logic_vector(min mod 10,4);
min_ten<=conv_std_logic_vector(min/10,4);
hour_one<=conv_std_logic_vector(hour mod 10,4);
hour_ten<=conv_std_logic_vector(hour/10,4);      
end;