alarm_clock.map.rpt

本文件是针对了解闹钟控制系统而写的一个VHDL源代码。

; POWER_UP_LEVEL ; Low   ; -    ; COUNTER_K[11] ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER_K[12] ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER_K[13] ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER_K[14] ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER_K[15] ;
; POWER_UP_LEVEL ; Low   ; -    ; CURR_STATE.s4 ;
; POWER_UP_LEVEL ; Low   ; -    ; CURR_STATE.s3 ;
; POWER_UP_LEVEL ; Low   ; -    ; CURR_STATE.s2 ;
; POWER_UP_LEVEL ; Low   ; -    ; CURR_STATE.s1 ;
; POWER_UP_LEVEL ; High  ; -    ; CURR_STATE.s0 ;
+----------------+-------+------+---------------+


+------------------------------------------------------+
; Source assignments for ALARM_COUNTER:U4              ;
+----------------+-------+------+----------------------+
; Assignment     ; Value ; From ; To                   ;
+----------------+-------+------+----------------------+
; POWER_UP_LEVEL ; Low   ; -    ; I_CURRENT_TIME[2][0] ;
; POWER_UP_LEVEL ; Low   ; -    ; I_CURRENT_TIME[1][3] ;
; POWER_UP_LEVEL ; Low   ; -    ; I_CURRENT_TIME[1][2] ;
; POWER_UP_LEVEL ; Low   ; -    ; I_CURRENT_TIME[1][1] ;
; POWER_UP_LEVEL ; Low   ; -    ; I_CURRENT_TIME[1][0] ;
; POWER_UP_LEVEL ; Low   ; -    ; I_CURRENT_TIME[0][3] ;
; POWER_UP_LEVEL ; Low   ; -    ; I_CURRENT_TIME[0][2] ;
; POWER_UP_LEVEL ; Low   ; -    ; I_CURRENT_TIME[0][1] ;
; POWER_UP_LEVEL ; Low   ; -    ; I_CURRENT_TIME[0][0] ;
; POWER_UP_LEVEL ; Low   ; -    ; I_CURRENT_TIME[2][1] ;
; POWER_UP_LEVEL ; Low   ; -    ; I_CURRENT_TIME[2][2] ;
; POWER_UP_LEVEL ; Low   ; -    ; I_CURRENT_TIME[2][3] ;
; POWER_UP_LEVEL ; Low   ; -    ; I_CURRENT_TIME[3][0] ;
; POWER_UP_LEVEL ; Low   ; -    ; I_CURRENT_TIME[3][1] ;
; POWER_UP_LEVEL ; Low   ; -    ; I_CURRENT_TIME[3][2] ;
; POWER_UP_LEVEL ; Low   ; -    ; I_CURRENT_TIME[3][3] ;
+----------------+-------+------+----------------------+


+----------------------------------------------------+
; Source assignments for FQ_DIVIDER:U7               ;
+----------------+-------+------+--------------------+
; Assignment     ; Value ; From ; To                 ;
+----------------+-------+------+--------------------+
; POWER_UP_LEVEL ; Low   ; -    ; DIVIDE_CLK:CNT[0]  ;
; POWER_UP_LEVEL ; Low   ; -    ; DIVIDE_CLK:CNT[1]  ;
; POWER_UP_LEVEL ; Low   ; -    ; DIVIDE_CLK:CNT[2]  ;
; POWER_UP_LEVEL ; Low   ; -    ; DIVIDE_CLK:CNT[3]  ;
; POWER_UP_LEVEL ; Low   ; -    ; DIVIDE_CLK:CNT[4]  ;
; POWER_UP_LEVEL ; Low   ; -    ; DIVIDE_CLK:CNT[5]  ;
; POWER_UP_LEVEL ; Low   ; -    ; DIVIDE_CLK:CNT[6]  ;
; POWER_UP_LEVEL ; Low   ; -    ; DIVIDE_CLK:CNT[7]  ;
; POWER_UP_LEVEL ; Low   ; -    ; DIVIDE_CLK:CNT[8]  ;
; POWER_UP_LEVEL ; Low   ; -    ; DIVIDE_CLK:CNT[9]  ;
; POWER_UP_LEVEL ; Low   ; -    ; DIVIDE_CLK:CNT[10] ;
; POWER_UP_LEVEL ; Low   ; -    ; DIVIDE_CLK:CNT[11] ;
; POWER_UP_LEVEL ; Low   ; -    ; DIVIDE_CLK:CNT[12] ;
; POWER_UP_LEVEL ; Low   ; -    ; DIVIDE_CLK:CNT[13] ;
; POWER_UP_LEVEL ; Low   ; -    ; DIVIDE_CLK:CNT[14] ;
; POWER_UP_LEVEL ; Low   ; -    ; DIVIDE_CLK:CNT[15] ;
+----------------+-------+------+--------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Dec 01 13:04:15 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off alarm_clock -c alarm_clock
Info: Found 2 design units, including 1 entities, in source file alarm_clock.vhd
    Info: Found design unit 1: ALARM_CLOCK-ART
    Info: Found entity 1: ALARM_CLOCK
Info: Found 2 design units, including 1 entities, in source file alarm_controller.vhd
    Info: Found design unit 1: ALARM_CONTROLLER-ART
    Info: Found entity 1: ALARM_CONTROLLER
Info: Found 2 design units, including 1 entities, in source file alarm_counter.vhd
    Info: Found design unit 1: ALARM_COUNTER-ART
    Info: Found entity 1: ALARM_COUNTER
Info: Found 2 design units, including 1 entities, in source file alarm_reg.vhd
    Info: Found design unit 1: ALARM_REG-ART
    Info: Found entity 1: ALARM_REG
Info: Found 2 design units, including 1 entities, in source file decoder.vhd
    Info: Found design unit 1: DECODER-ART
    Info: Found entity 1: DECODER
Info: Found 2 design units, including 1 entities, in source file display_driver.vhd
    Info: Found design unit 1: DISPLAY_DRIVER-ART
    Info: Found entity 1: DISPLAY_DRIVER
Info: Found 2 design units, including 1 entities, in source file fq_divider.vhd
    Info: Found design unit 1: FQ_DIVIDER-ART
    Info: Found entity 1: FQ_DIVIDER
Info: Found 2 design units, including 1 entities, in source file key_buffer.vhd
    Info: Found design unit 1: KEY_BUFFER-ART
    Info: Found entity 1: KEY_BUFFER
Info: Found 1 design units, including 0 entities, in source file p_alarm.vhd
    Info: Found design unit 1: P_ALARM
Info: Found 1 design units, including 1 entities, in source file alarmclock.bdf
    Info: Found entity 1: alarmclock
Info: Elaborating entity "alarm_clock" for the top level hierarchy
Info: Elaborating entity "DECODER" using architecture "A:art" for hierarchy "DECODER:U1"
Info: Elaborating entity "KEY_BUFFER" using architecture "A:art" for hierarchy "KEY_BUFFER:U2"
Info: Elaborating entity "ALARM_CONTROLLER" using architecture "A:art" for hierarchy "ALARM_CONTROLLER:U3"
Info: Elaborating entity "ALARM_COUNTER" using architecture "A:art" for hierarchy "ALARM_COUNTER:U4"
Warning (10492): VHDL Process Statement warning at alarm_counter.vhd(22): signal "NEW_CURRENT_TIME" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "ALARM_REG" using architecture "A:art" for hierarchy "ALARM_REG:U5"
Info: Elaborating entity "DISPLAY_DRIVER" using architecture "A:art" for hierarchy "DISPLAY_DRIVER:U6"
Warning (10631): VHDL Process Statement warning at display_driver.vhd(16): inferring latch(es) for signal or variable "DISPLAY_TIME", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(16): inferred latch for "DISPLAY_TIME[0][0]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(16): inferred latch for "DISPLAY_TIME[0][1]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(16): inferred latch for "DISPLAY_TIME[0][2]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(16): inferred latch for "DISPLAY_TIME[0][3]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(16): inferred latch for "DISPLAY_TIME[1][0]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(16): inferred latch for "DISPLAY_TIME[1][1]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(16): inferred latch for "DISPLAY_TIME[1][2]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(16): inferred latch for "DISPLAY_TIME[1][3]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(16): inferred latch for "DISPLAY_TIME[2][0]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(16): inferred latch for "DISPLAY_TIME[2][1]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(16): inferred latch for "DISPLAY_TIME[2][2]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(16): inferred latch for "DISPLAY_TIME[2][3]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(16): inferred latch for "DISPLAY_TIME[3][0]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(16): inferred latch for "DISPLAY_TIME[3][1]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(16): inferred latch for "DISPLAY_TIME[3][2]"
Info (10041): Verilog HDL or VHDL info at display_driver.vhd(16): inferred latch for "DISPLAY_TIME[3][3]"
Info: Elaborating entity "FQ_DIVIDER" using architecture "A:art" for hierarchy "FQ_DIVIDER:U7"
Info: State machine "|ALARM_CLOCK|ALARM_CONTROLLER:U3|CURR_STATE" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|ALARM_CLOCK|ALARM_CONTROLLER:U3|CURR_STATE"
Info: Encoding result for state machine "|ALARM_CLOCK|ALARM_CONTROLLER:U3|CURR_STATE"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "ALARM_CONTROLLER:U3|CURR_STATE.s4"
        Info: Encoded state bit "ALARM_CONTROLLER:U3|CURR_STATE.s3"
        Info: Encoded state bit "ALARM_CONTROLLER:U3|CURR_STATE.s2"
        Info: Encoded state bit "ALARM_CONTROLLER:U3|CURR_STATE.s1"
        Info: Encoded state bit "ALARM_CONTROLLER:U3|CURR_STATE.s0"
    Info: State "|ALARM_CLOCK|ALARM_CONTROLLER:U3|CURR_STATE.s0" uses code string "00000"
    Info: State "|ALARM_CLOCK|ALARM_CONTROLLER:U3|CURR_STATE.s1" uses code string "00011"
    Info: State "|ALARM_CLOCK|ALARM_CONTROLLER:U3|CURR_STATE.s2" uses code string "00101"
    Info: State "|ALARM_CLOCK|ALARM_CONTROLLER:U3|CURR_STATE.s3" uses code string "01001"
    Info: State "|ALARM_CLOCK|ALARM_CONTROLLER:U3|CURR_STATE.s4" uses code string "10001"
Info: Implemented 288 device resources after synthesis - the final resource count might be different
    Info: Implemented 15 input pins
    Info: Implemented 29 output pins
    Info: Implemented 244 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Mon Dec 01 13:04:21 2008
    Info: Elapsed time: 00:00:07