fq_divider.vhd

来自「本文件是针对了解闹钟控制系统而写的一个VHDL源代码。」· VHDL 代码 · 共 32 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.P_ALARM.ALL;
ENTITY FQ_DIVIDER IS
   PORT(
      CLK_IN      :IN  STD_LOGIC;
      RESET       :IN  STD_LOGIC;
      CLK_OUT     :OUT STD_LOGIC );
END ENTITY FQ_DIVIDER;
ARCHITECTURE ART OF FQ_DIVIDER IS
CONSTANT DIVIDE_PERIOD : T_SHORT := 6000;
   BEGIN
   DIVIDE_CLK: PROCESS(CLK_IN,RESET)
      VARIABLE CNT : T_SHORT;
   BEGIN
  IF (RESET = '1') THEN
      CNT := 0;
      CLK_OUT <= '0';
  ELSIF RISING_EDGE(CLK_IN) THEN
      IF (CNT < (DIVIDE_PERIOD/2)) THEN
      CLK_OUT <= '1';
CNT := CNT + 1;
      ELSIF (CNT < (DIVIDE_PERIOD-1)) THEN
    CLK_OUT <= '0';
    CNT := CNT + 1;
  ELSE
    CNT := 0;
      END IF;
   END IF;
  END PROCESS; -- DIVIDE CLK
END ARCHITECTURE ART;