alarm_clock.tan.qmsg

本文件是针对了解闹钟控制系统而写的一个VHDL源代码。

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK SOUND_ALARM ALARM_COUNTER:U4\|I_CURRENT_TIME\[2\]\[1\] 16.686 ns register " "Info: tco from clock \"CLK\" to destination pin \"SOUND_ALARM\" through register \"ALARM_COUNTER:U4\|I_CURRENT_TIME\[2\]\[1\]\" is 16.686 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.408 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 7.408 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 72 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 72; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/闹钟控制系统/alarm_clock.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.935 ns) 3.006 ns FQ_DIVIDER:U7\|CLK_OUT 2 REG LC_X26_Y6_N4 17 " "Info: 2: + IC(0.602 ns) + CELL(0.935 ns) = 3.006 ns; Loc. = LC_X26_Y6_N4; Fanout = 17; REG Node = 'FQ_DIVIDER:U7\|CLK_OUT'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.537 ns" { CLK FQ_DIVIDER:U7|CLK_OUT } "NODE_NAME" } } { "fq_divider.vhd" "" { Text "E:/闹钟控制系统/fq_divider.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.691 ns) + CELL(0.711 ns) 7.408 ns ALARM_COUNTER:U4\|I_CURRENT_TIME\[2\]\[1\] 3 REG LC_X8_Y11_N5 6 " "Info: 3: + IC(3.691 ns) + CELL(0.711 ns) = 7.408 ns; Loc. = LC_X8_Y11_N5; Fanout = 6; REG Node = 'ALARM_COUNTER:U4\|I_CURRENT_TIME\[2\]\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.402 ns" { FQ_DIVIDER:U7|CLK_OUT ALARM_COUNTER:U4|I_CURRENT_TIME[2][1] } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/闹钟控制系统/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.05 % ) " "Info: Total cell delay = 3.115 ns ( 42.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.293 ns ( 57.95 % ) " "Info: Total interconnect delay = 4.293 ns ( 57.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.408 ns" { CLK FQ_DIVIDER:U7|CLK_OUT ALARM_COUNTER:U4|I_CURRENT_TIME[2][1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.408 ns" { CLK CLK~out0 FQ_DIVIDER:U7|CLK_OUT ALARM_COUNTER:U4|I_CURRENT_TIME[2][1] } { 0.000ns 0.000ns 0.602ns 3.691ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "alarm_counter.vhd" "" { Text "E:/闹钟控制系统/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.054 ns + Longest register pin " "Info: + Longest register to pin delay is 9.054 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ALARM_COUNTER:U4\|I_CURRENT_TIME\[2\]\[1\] 1 REG LC_X8_Y11_N5 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y11_N5; Fanout = 6; REG Node = 'ALARM_COUNTER:U4\|I_CURRENT_TIME\[2\]\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ALARM_COUNTER:U4|I_CURRENT_TIME[2][1] } "NODE_NAME" } } { "alarm_counter.vhd" "" { Text "E:/闹钟控制系统/alarm_counter.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.623 ns) + CELL(0.590 ns) 2.213 ns DISPLAY_DRIVER:U6\|CTRL~114 2 COMB LC_X10_Y10_N8 1 " "Info: 2: + IC(1.623 ns) + CELL(0.590 ns) = 2.213 ns; Loc. = LC_X10_Y10_N8; Fanout = 1; COMB Node = 'DISPLAY_DRIVER:U6\|CTRL~114'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.213 ns" { ALARM_COUNTER:U4|I_CURRENT_TIME[2][1] DISPLAY_DRIVER:U6|CTRL~114 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.273 ns) + CELL(0.590 ns) 4.076 ns DISPLAY_DRIVER:U6\|CTRL~118 3 COMB LC_X10_Y11_N7 1 " "Info: 3: + IC(1.273 ns) + CELL(0.590 ns) = 4.076 ns; Loc. = LC_X10_Y11_N7; Fanout = 1; COMB Node = 'DISPLAY_DRIVER:U6\|CTRL~118'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.863 ns" { DISPLAY_DRIVER:U6|CTRL~114 DISPLAY_DRIVER:U6|CTRL~118 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.133 ns) + CELL(0.442 ns) 5.651 ns DISPLAY_DRIVER:U6\|CTRL~2 4 COMB LC_X9_Y12_N2 1 " "Info: 4: + IC(1.133 ns) + CELL(0.442 ns) = 5.651 ns; Loc. = LC_X9_Y12_N2; Fanout = 1; COMB Node = 'DISPLAY_DRIVER:U6\|CTRL~2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.575 ns" { DISPLAY_DRIVER:U6|CTRL~118 DISPLAY_DRIVER:U6|CTRL~2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.295 ns) + CELL(2.108 ns) 9.054 ns SOUND_ALARM 5 PIN PIN_132 0 " "Info: 5: + IC(1.295 ns) + CELL(2.108 ns) = 9.054 ns; Loc. = PIN_132; Fanout = 0; PIN Node = 'SOUND_ALARM'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.403 ns" { DISPLAY_DRIVER:U6|CTRL~2 SOUND_ALARM } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/闹钟控制系统/alarm_clock.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.730 ns ( 41.20 % ) " "Info: Total cell delay = 3.730 ns ( 41.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.324 ns ( 58.80 % ) " "Info: Total interconnect delay = 5.324 ns ( 58.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.054 ns" { ALARM_COUNTER:U4|I_CURRENT_TIME[2][1] DISPLAY_DRIVER:U6|CTRL~114 DISPLAY_DRIVER:U6|CTRL~118 DISPLAY_DRIVER:U6|CTRL~2 SOUND_ALARM } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.054 ns" { ALARM_COUNTER:U4|I_CURRENT_TIME[2][1] DISPLAY_DRIVER:U6|CTRL~114 DISPLAY_DRIVER:U6|CTRL~118 DISPLAY_DRIVER:U6|CTRL~2 SOUND_ALARM } { 0.000ns 1.623ns 1.273ns 1.133ns 1.295ns } { 0.000ns 0.590ns 0.590ns 0.442ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.408 ns" { CLK FQ_DIVIDER:U7|CLK_OUT ALARM_COUNTER:U4|I_CURRENT_TIME[2][1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.408 ns" { CLK CLK~out0 FQ_DIVIDER:U7|CLK_OUT ALARM_COUNTER:U4|I_CURRENT_TIME[2][1] } { 0.000ns 0.000ns 0.602ns 3.691ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.054 ns" { ALARM_COUNTER:U4|I_CURRENT_TIME[2][1] DISPLAY_DRIVER:U6|CTRL~114 DISPLAY_DRIVER:U6|CTRL~118 DISPLAY_DRIVER:U6|CTRL~2 SOUND_ALARM } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.054 ns" { ALARM_COUNTER:U4|I_CURRENT_TIME[2][1] DISPLAY_DRIVER:U6|CTRL~114 DISPLAY_DRIVER:U6|CTRL~118 DISPLAY_DRIVER:U6|CTRL~2 SOUND_ALARM } { 0.000ns 1.623ns 1.273ns 1.133ns 1.295ns } { 0.000ns 0.590ns 0.590ns 0.442ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "ALARM_BUTTON DISPLAY\[3\]\[2\] 19.779 ns Longest " "Info: Longest tpd from source pin \"ALARM_BUTTON\" to destination pin \"DISPLAY\[3\]\[2\]\" is 19.779 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ALARM_BUTTON 1 PIN PIN_83 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_83; Fanout = 8; PIN Node = 'ALARM_BUTTON'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ALARM_BUTTON } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/闹钟控制系统/alarm_clock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.557 ns) + CELL(0.590 ns) 8.616 ns ALARM_CONTROLLER:U3\|Selector6~35 2 COMB LC_X11_Y9_N9 32 " "Info: 2: + IC(6.557 ns) + CELL(0.590 ns) = 8.616 ns; Loc. = LC_X11_Y9_N9; Fanout = 32; COMB Node = 'ALARM_CONTROLLER:U3\|Selector6~35'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.147 ns" { ALARM_BUTTON ALARM_CONTROLLER:U3|Selector6~35 } "NODE_NAME" } } { "alarm_controller.vhd" "" { Text "E:/闹钟控制系统/alarm_controller.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.691 ns) + CELL(0.590 ns) 10.897 ns DISPLAY_DRIVER:U6\|comb~3381 3 COMB LC_X9_Y10_N0 1 " "Info: 3: + IC(1.691 ns) + CELL(0.590 ns) = 10.897 ns; Loc. = LC_X9_Y10_N0; Fanout = 1; COMB Node = 'DISPLAY_DRIVER:U6\|comb~3381'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.281 ns" { ALARM_CONTROLLER:U3|Selector6~35 DISPLAY_DRIVER:U6|comb~3381 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.291 ns) + CELL(0.590 ns) 13.778 ns DISPLAY_DRIVER:U6\|comb~3382 4 COMB LC_X9_Y10_N6 7 " "Info: 4: + IC(2.291 ns) + CELL(0.590 ns) = 13.778 ns; Loc. = LC_X9_Y10_N6; Fanout = 7; COMB Node = 'DISPLAY_DRIVER:U6\|comb~3382'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.881 ns" { DISPLAY_DRIVER:U6|comb~3381 DISPLAY_DRIVER:U6|comb~3382 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.254 ns) + CELL(0.114 ns) 15.146 ns DISPLAY_DRIVER:U6\|Mux4~98 5 COMB LC_X11_Y10_N4 1 " "Info: 5: + IC(1.254 ns) + CELL(0.114 ns) = 15.146 ns; Loc. = LC_X11_Y10_N4; Fanout = 1; COMB Node = 'DISPLAY_DRIVER:U6\|Mux4~98'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.368 ns" { DISPLAY_DRIVER:U6|comb~3382 DISPLAY_DRIVER:U6|Mux4~98 } "NODE_NAME" } } { "display_driver.vhd" "" { Text "E:/闹钟控制系统/display_driver.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.509 ns) + CELL(2.124 ns) 19.779 ns DISPLAY\[3\]\[2\] 6 PIN PIN_99 0 " "Info: 6: + IC(2.509 ns) + CELL(2.124 ns) = 19.779 ns; Loc. = PIN_99; Fanout = 0; PIN Node = 'DISPLAY\[3\]\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.633 ns" { DISPLAY_DRIVER:U6|Mux4~98 DISPLAY[3][2] } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/闹钟控制系统/alarm_clock.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.477 ns ( 27.69 % ) " "Info: Total cell delay = 5.477 ns ( 27.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "14.302 ns ( 72.31 % ) " "Info: Total interconnect delay = 14.302 ns ( 72.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.779 ns" { ALARM_BUTTON ALARM_CONTROLLER:U3|Selector6~35 DISPLAY_DRIVER:U6|comb~3381 DISPLAY_DRIVER:U6|comb~3382 DISPLAY_DRIVER:U6|Mux4~98 DISPLAY[3][2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "19.779 ns" { ALARM_BUTTON ALARM_BUTTON~out0 ALARM_CONTROLLER:U3|Selector6~35 DISPLAY_DRIVER:U6|comb~3381 DISPLAY_DRIVER:U6|comb~3382 DISPLAY_DRIVER:U6|Mux4~98 DISPLAY[3][2] } { 0.000ns 0.000ns 6.557ns 1.691ns 2.291ns 1.254ns 2.509ns } { 0.000ns 1.469ns 0.590ns 0.590ns 0.590ns 0.114ns 2.124ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "ALARM_CONTROLLER:U3\|CURR_STATE.s4 KEY_DOWN CLK -0.436 ns register " "Info: th for register \"ALARM_CONTROLLER:U3\|CURR_STATE.s4\" (data pin = \"KEY_DOWN\", clock pin = \"CLK\") is -0.436 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.740 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 72 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 72; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/闹钟控制系统/alarm_clock.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.711 ns) 2.740 ns ALARM_CONTROLLER:U3\|CURR_STATE.s4 2 REG LC_X11_Y8_N3 4 " "Info: 2: + IC(0.560 ns) + CELL(0.711 ns) = 2.740 ns; Loc. = LC_X11_Y8_N3; Fanout = 4; REG Node = 'ALARM_CONTROLLER:U3\|CURR_STATE.s4'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.271 ns" { CLK ALARM_CONTROLLER:U3|CURR_STATE.s4 } "NODE_NAME" } } { "alarm_controller.vhd" "" { Text "E:/闹钟控制系统/alarm_controller.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.56 % ) " "Info: Total cell delay = 2.180 ns ( 79.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 20.44 % ) " "Info: Total interconnect delay = 0.560 ns ( 20.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { CLK ALARM_CONTROLLER:U3|CURR_STATE.s4 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { CLK CLK~out0 ALARM_CONTROLLER:U3|CURR_STATE.s4 } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "alarm_controller.vhd" "" { Text "E:/闹钟控制系统/alarm_controller.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.191 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns KEY_DOWN 1 CLK PIN_16 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 25; CLK Node = 'KEY_DOWN'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KEY_DOWN } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/闹钟控制系统/alarm_clock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.244 ns) + CELL(0.478 ns) 3.191 ns ALARM_CONTROLLER:U3\|CURR_STATE.s4 2 REG LC_X11_Y8_N3 4 " "Info: 2: + IC(1.244 ns) + CELL(0.478 ns) = 3.191 ns; Loc. = LC_X11_Y8_N3; Fanout = 4; REG Node = 'ALARM_CONTROLLER:U3\|CURR_STATE.s4'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.722 ns" { KEY_DOWN ALARM_CONTROLLER:U3|CURR_STATE.s4 } "NODE_NAME" } } { "alarm_controller.vhd" "" { Text "E:/闹钟控制系统/alarm_controller.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.947 ns ( 61.02 % ) " "Info: Total cell delay = 1.947 ns ( 61.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.244 ns ( 38.98 % ) " "Info: Total interconnect delay = 1.244 ns ( 38.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.191 ns" { KEY_DOWN ALARM_CONTROLLER:U3|CURR_STATE.s4 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.191 ns" { KEY_DOWN KEY_DOWN~out0 ALARM_CONTROLLER:U3|CURR_STATE.s4 } { 0.000ns 0.000ns 1.244ns } { 0.000ns 1.469ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { CLK ALARM_CONTROLLER:U3|CURR_STATE.s4 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { CLK CLK~out0 ALARM_CONTROLLER:U3|CURR_STATE.s4 } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.191 ns" { KEY_DOWN ALARM_CONTROLLER:U3|CURR_STATE.s4 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.191 ns" { KEY_DOWN KEY_DOWN~out0 ALARM_CONTROLLER:U3|CURR_STATE.s4 } { 0.000ns 0.000ns 1.244ns } { 0.000ns 1.469ns 0.478ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 01 13:04:45 2008 " "Info: Processing ended: Mon Dec 01 13:04:45 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}