alarm_clock.tan.qmsg

本文件是针对了解闹钟控制系统而写的一个VHDL源代码。

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "FQ_DIVIDER:U7\|CLK_OUT " "Info: Detected ripple clock \"FQ_DIVIDER:U7\|CLK_OUT\" as buffer" {  } { { "fq_divider.vhd" "" { Text "E:/闹钟控制系统/fq_divider.vhd" 8 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FQ_DIVIDER:U7\|CLK_OUT" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "KEY_DOWN register register KEY_BUFFER:U2\|N_T\[0\]\[1\] KEY_BUFFER:U2\|N_T\[1\]\[1\] 275.03 MHz Internal " "Info: Clock \"KEY_DOWN\" Internal fmax is restricted to 275.03 MHz between source register \"KEY_BUFFER:U2\|N_T\[0\]\[1\]\" and destination register \"KEY_BUFFER:U2\|N_T\[1\]\[1\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.695 ns + Longest register register " "Info: + Longest register to register delay is 0.695 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns KEY_BUFFER:U2\|N_T\[0\]\[1\] 1 REG LC_X10_Y10_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y10_N7; Fanout = 4; REG Node = 'KEY_BUFFER:U2\|N_T\[0\]\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KEY_BUFFER:U2|N_T[0][1] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/闹钟控制系统/key_buffer.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.580 ns) + CELL(0.115 ns) 0.695 ns KEY_BUFFER:U2\|N_T\[1\]\[1\] 2 REG LC_X10_Y10_N9 4 " "Info: 2: + IC(0.580 ns) + CELL(0.115 ns) = 0.695 ns; Loc. = LC_X10_Y10_N9; Fanout = 4; REG Node = 'KEY_BUFFER:U2\|N_T\[1\]\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.695 ns" { KEY_BUFFER:U2|N_T[0][1] KEY_BUFFER:U2|N_T[1][1] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/闹钟控制系统/key_buffer.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns ( 16.55 % ) " "Info: Total cell delay = 0.115 ns ( 16.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.580 ns ( 83.45 % ) " "Info: Total interconnect delay = 0.580 ns ( 83.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.695 ns" { KEY_BUFFER:U2|N_T[0][1] KEY_BUFFER:U2|N_T[1][1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.695 ns" { KEY_BUFFER:U2|N_T[0][1] KEY_BUFFER:U2|N_T[1][1] } { 0.000ns 0.580ns } { 0.000ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "KEY_DOWN destination 2.768 ns + Shortest register " "Info: + Shortest clock path from clock \"KEY_DOWN\" to destination register is 2.768 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns KEY_DOWN 1 CLK PIN_16 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 25; CLK Node = 'KEY_DOWN'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KEY_DOWN } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/闹钟控制系统/alarm_clock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.588 ns) + CELL(0.711 ns) 2.768 ns KEY_BUFFER:U2\|N_T\[1\]\[1\] 2 REG LC_X10_Y10_N9 4 " "Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X10_Y10_N9; Fanout = 4; REG Node = 'KEY_BUFFER:U2\|N_T\[1\]\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.299 ns" { KEY_DOWN KEY_BUFFER:U2|N_T[1][1] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/闹钟控制系统/key_buffer.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.76 % ) " "Info: Total cell delay = 2.180 ns ( 78.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.588 ns ( 21.24 % ) " "Info: Total interconnect delay = 0.588 ns ( 21.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { KEY_DOWN KEY_BUFFER:U2|N_T[1][1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { KEY_DOWN KEY_DOWN~out0 KEY_BUFFER:U2|N_T[1][1] } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "KEY_DOWN source 2.768 ns - Longest register " "Info: - Longest clock path from clock \"KEY_DOWN\" to source register is 2.768 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns KEY_DOWN 1 CLK PIN_16 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 25; CLK Node = 'KEY_DOWN'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KEY_DOWN } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/闹钟控制系统/alarm_clock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.588 ns) + CELL(0.711 ns) 2.768 ns KEY_BUFFER:U2\|N_T\[0\]\[1\] 2 REG LC_X10_Y10_N7 4 " "Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X10_Y10_N7; Fanout = 4; REG Node = 'KEY_BUFFER:U2\|N_T\[0\]\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.299 ns" { KEY_DOWN KEY_BUFFER:U2|N_T[0][1] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/闹钟控制系统/key_buffer.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.76 % ) " "Info: Total cell delay = 2.180 ns ( 78.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.588 ns ( 21.24 % ) " "Info: Total interconnect delay = 0.588 ns ( 21.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { KEY_DOWN KEY_BUFFER:U2|N_T[0][1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { KEY_DOWN KEY_DOWN~out0 KEY_BUFFER:U2|N_T[0][1] } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { KEY_DOWN KEY_BUFFER:U2|N_T[1][1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { KEY_DOWN KEY_DOWN~out0 KEY_BUFFER:U2|N_T[1][1] } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { KEY_DOWN KEY_BUFFER:U2|N_T[0][1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { KEY_DOWN KEY_DOWN~out0 KEY_BUFFER:U2|N_T[0][1] } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "key_buffer.vhd" "" { Text "E:/闹钟控制系统/key_buffer.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "key_buffer.vhd" "" { Text "E:/闹钟控制系统/key_buffer.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.695 ns" { KEY_BUFFER:U2|N_T[0][1] KEY_BUFFER:U2|N_T[1][1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.695 ns" { KEY_BUFFER:U2|N_T[0][1] KEY_BUFFER:U2|N_T[1][1] } { 0.000ns 0.580ns } { 0.000ns 0.115ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { KEY_DOWN KEY_BUFFER:U2|N_T[1][1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { KEY_DOWN KEY_DOWN~out0 KEY_BUFFER:U2|N_T[1][1] } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { KEY_DOWN KEY_BUFFER:U2|N_T[0][1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { KEY_DOWN KEY_DOWN~out0 KEY_BUFFER:U2|N_T[0][1] } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KEY_BUFFER:U2|N_T[1][1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { KEY_BUFFER:U2|N_T[1][1] } {  } {  } } } { "key_buffer.vhd" "" { Text "E:/闹钟控制系统/key_buffer.vhd" 15 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register FQ_DIVIDER:U7\|\\DIVIDE_CLK:CNT\[0\] register FQ_DIVIDER:U7\|\\DIVIDE_CLK:CNT\[7\] 176.09 MHz 5.679 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 176.09 MHz between source register \"FQ_DIVIDER:U7\|\\DIVIDE_CLK:CNT\[0\]\" and destination register \"FQ_DIVIDER:U7\|\\DIVIDE_CLK:CNT\[7\]\" (period= 5.679 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.418 ns + Longest register register " "Info: + Longest register to register delay is 5.418 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FQ_DIVIDER:U7\|\\DIVIDE_CLK:CNT\[0\] 1 REG LC_X25_Y7_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y7_N2; Fanout = 4; REG Node = 'FQ_DIVIDER:U7\|\\DIVIDE_CLK:CNT\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[0] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.551 ns) + CELL(0.590 ns) 1.141 ns FQ_DIVIDER:U7\|LessThan1~453 2 COMB LC_X25_Y7_N0 1 " "Info: 2: + IC(0.551 ns) + CELL(0.590 ns) = 1.141 ns; Loc. = LC_X25_Y7_N0; Fanout = 1; COMB Node = 'FQ_DIVIDER:U7\|LessThan1~453'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.141 ns" { FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[0] FQ_DIVIDER:U7|LessThan1~453 } "NODE_NAME" } } { "fq_divider.vhd" "" { Text "E:/闹钟控制系统/fq_divider.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 1.437 ns FQ_DIVIDER:U7\|LessThan1~454 3 COMB LC_X25_Y7_N1 1 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 1.437 ns; Loc. = LC_X25_Y7_N1; Fanout = 1; COMB Node = 'FQ_DIVIDER:U7\|LessThan1~454'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { FQ_DIVIDER:U7|LessThan1~453 FQ_DIVIDER:U7|LessThan1~454 } "NODE_NAME" } } { "fq_divider.vhd" "" { Text "E:/闹钟控制系统/fq_divider.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.213 ns) + CELL(0.114 ns) 2.764 ns FQ_DIVIDER:U7\|LessThan1~455 4 COMB LC_X25_Y6_N8 1 " "Info: 4: + IC(1.213 ns) + CELL(0.114 ns) = 2.764 ns; Loc. = LC_X25_Y6_N8; Fanout = 1; COMB Node = 'FQ_DIVIDER:U7\|LessThan1~455'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.327 ns" { FQ_DIVIDER:U7|LessThan1~454 FQ_DIVIDER:U7|LessThan1~455 } "NODE_NAME" } } { "fq_divider.vhd" "" { Text "E:/闹钟控制系统/fq_divider.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 3.060 ns FQ_DIVIDER:U7\|LessThan1~456 5 COMB LC_X25_Y6_N9 17 " "Info: 5: + IC(0.182 ns) + CELL(0.114 ns) = 3.060 ns; Loc. = LC_X25_Y6_N9; Fanout = 17; COMB Node = 'FQ_DIVIDER:U7\|LessThan1~456'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { FQ_DIVIDER:U7|LessThan1~455 FQ_DIVIDER:U7|LessThan1~456 } "NODE_NAME" } } { "fq_divider.vhd" "" { Text "E:/闹钟控制系统/fq_divider.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.246 ns) + CELL(1.112 ns) 5.418 ns FQ_DIVIDER:U7\|\\DIVIDE_CLK:CNT\[7\] 6 REG LC_X25_Y7_N9 4 " "Info: 6: + IC(1.246 ns) + CELL(1.112 ns) = 5.418 ns; Loc. = LC_X25_Y7_N9; Fanout = 4; REG Node = 'FQ_DIVIDER:U7\|\\DIVIDE_CLK:CNT\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.358 ns" { FQ_DIVIDER:U7|LessThan1~456 FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[7] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.044 ns ( 37.73 % ) " "Info: Total cell delay = 2.044 ns ( 37.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.374 ns ( 62.27 % ) " "Info: Total interconnect delay = 3.374 ns ( 62.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.418 ns" { FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[0] FQ_DIVIDER:U7|LessThan1~453 FQ_DIVIDER:U7|LessThan1~454 FQ_DIVIDER:U7|LessThan1~455 FQ_DIVIDER:U7|LessThan1~456 FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.418 ns" { FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[0] FQ_DIVIDER:U7|LessThan1~453 FQ_DIVIDER:U7|LessThan1~454 FQ_DIVIDER:U7|LessThan1~455 FQ_DIVIDER:U7|LessThan1~456 FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[7] } { 0.000ns 0.551ns 0.182ns 1.213ns 0.182ns 1.246ns } { 0.000ns 0.590ns 0.114ns 0.114ns 0.114ns 1.112ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.782 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 72 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 72; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/闹钟控制系统/alarm_clock.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns FQ_DIVIDER:U7\|\\DIVIDE_CLK:CNT\[7\] 2 REG LC_X25_Y7_N9 4 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X25_Y7_N9; Fanout = 4; REG Node = 'FQ_DIVIDER:U7\|\\DIVIDE_CLK:CNT\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { CLK FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[7] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { CLK FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { CLK CLK~out0 FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[7] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.782 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 72 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 72; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/闹钟控制系统/alarm_clock.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns FQ_DIVIDER:U7\|\\DIVIDE_CLK:CNT\[0\] 2 REG LC_X25_Y7_N2 4 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X25_Y7_N2; Fanout = 4; REG Node = 'FQ_DIVIDER:U7\|\\DIVIDE_CLK:CNT\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { CLK FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[0] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { CLK FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { CLK CLK~out0 FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[0] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { CLK FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { CLK CLK~out0 FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[7] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { CLK FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { CLK CLK~out0 FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[0] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.418 ns" { FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[0] FQ_DIVIDER:U7|LessThan1~453 FQ_DIVIDER:U7|LessThan1~454 FQ_DIVIDER:U7|LessThan1~455 FQ_DIVIDER:U7|LessThan1~456 FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.418 ns" { FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[0] FQ_DIVIDER:U7|LessThan1~453 FQ_DIVIDER:U7|LessThan1~454 FQ_DIVIDER:U7|LessThan1~455 FQ_DIVIDER:U7|LessThan1~456 FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[7] } { 0.000ns 0.551ns 0.182ns 1.213ns 0.182ns 1.246ns } { 0.000ns 0.590ns 0.114ns 0.114ns 0.114ns 1.112ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { CLK FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[7] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { CLK CLK~out0 FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[7] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { CLK FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { CLK CLK~out0 FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[0] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "KEY_BUFFER:U2\|N_T\[0\]\[0\] KEYPAD\[3\] KEY_DOWN 8.454 ns register " "Info: tsu for register \"KEY_BUFFER:U2\|N_T\[0\]\[0\]\" (data pin = \"KEYPAD\[3\]\", clock pin = \"KEY_DOWN\") is 8.454 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.185 ns + Longest pin register " "Info: + Longest pin to register delay is 11.185 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns KEYPAD\[3\] 1 PIN PIN_122 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_122; Fanout = 5; PIN Node = 'KEYPAD\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KEYPAD[3] } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/闹钟控制系统/alarm_clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.931 ns) + CELL(0.590 ns) 7.996 ns DECODER:U1\|WideOr2~69 2 COMB LC_X10_Y12_N4 1 " "Info: 2: + IC(5.931 ns) + CELL(0.590 ns) = 7.996 ns; Loc. = LC_X10_Y12_N4; Fanout = 1; COMB Node = 'DECODER:U1\|WideOr2~69'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.521 ns" { KEYPAD[3] DECODER:U1|WideOr2~69 } "NODE_NAME" } } { "decoder.vhd" "" { Text "E:/闹钟控制系统/decoder.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.292 ns) 8.731 ns DECODER:U1\|WideOr2~68 3 COMB LC_X10_Y12_N8 1 " "Info: 3: + IC(0.443 ns) + CELL(0.292 ns) = 8.731 ns; Loc. = LC_X10_Y12_N8; Fanout = 1; COMB Node = 'DECODER:U1\|WideOr2~68'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.735 ns" { DECODER:U1|WideOr2~69 DECODER:U1|WideOr2~68 } "NODE_NAME" } } { "decoder.vhd" "" { Text "E:/闹钟控制系统/decoder.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.292 ns) 9.466 ns DECODER:U1\|WideOr2~65 4 COMB LC_X10_Y12_N3 1 " "Info: 4: + IC(0.443 ns) + CELL(0.292 ns) = 9.466 ns; Loc. = LC_X10_Y12_N3; Fanout = 1; COMB Node = 'DECODER:U1\|WideOr2~65'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.735 ns" { DECODER:U1|WideOr2~68 DECODER:U1|WideOr2~65 } "NODE_NAME" } } { "decoder.vhd" "" { Text "E:/闹钟控制系统/decoder.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.241 ns) + CELL(0.478 ns) 11.185 ns KEY_BUFFER:U2\|N_T\[0\]\[0\] 5 REG LC_X10_Y11_N2 4 " "Info: 5: + IC(1.241 ns) + CELL(0.478 ns) = 11.185 ns; Loc. = LC_X10_Y11_N2; Fanout = 4; REG Node = 'KEY_BUFFER:U2\|N_T\[0\]\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.719 ns" { DECODER:U1|WideOr2~65 KEY_BUFFER:U2|N_T[0][0] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/闹钟控制系统/key_buffer.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.127 ns ( 27.96 % ) " "Info: Total cell delay = 3.127 ns ( 27.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.058 ns ( 72.04 % ) " "Info: Total interconnect delay = 8.058 ns ( 72.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.185 ns" { KEYPAD[3] DECODER:U1|WideOr2~69 DECODER:U1|WideOr2~68 DECODER:U1|WideOr2~65 KEY_BUFFER:U2|N_T[0][0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.185 ns" { KEYPAD[3] KEYPAD[3]~out0 DECODER:U1|WideOr2~69 DECODER:U1|WideOr2~68 DECODER:U1|WideOr2~65 KEY_BUFFER:U2|N_T[0][0] } { 0.000ns 0.000ns 5.931ns 0.443ns 0.443ns 1.241ns } { 0.000ns 1.475ns 0.590ns 0.292ns 0.292ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "key_buffer.vhd" "" { Text "E:/闹钟控制系统/key_buffer.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "KEY_DOWN destination 2.768 ns - Shortest register " "Info: - Shortest clock path from clock \"KEY_DOWN\" to destination register is 2.768 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns KEY_DOWN 1 CLK PIN_16 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 25; CLK Node = 'KEY_DOWN'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KEY_DOWN } "NODE_NAME" } } { "alarm_clock.vhd" "" { Text "E:/闹钟控制系统/alarm_clock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.588 ns) + CELL(0.711 ns) 2.768 ns KEY_BUFFER:U2\|N_T\[0\]\[0\] 2 REG LC_X10_Y11_N2 4 " "Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X10_Y11_N2; Fanout = 4; REG Node = 'KEY_BUFFER:U2\|N_T\[0\]\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.299 ns" { KEY_DOWN KEY_BUFFER:U2|N_T[0][0] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/闹钟控制系统/key_buffer.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.76 % ) " "Info: Total cell delay = 2.180 ns ( 78.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.588 ns ( 21.24 % ) " "Info: Total interconnect delay = 0.588 ns ( 21.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { KEY_DOWN KEY_BUFFER:U2|N_T[0][0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { KEY_DOWN KEY_DOWN~out0 KEY_BUFFER:U2|N_T[0][0] } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.185 ns" { KEYPAD[3] DECODER:U1|WideOr2~69 DECODER:U1|WideOr2~68 DECODER:U1|WideOr2~65 KEY_BUFFER:U2|N_T[0][0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.185 ns" { KEYPAD[3] KEYPAD[3]~out0 DECODER:U1|WideOr2~69 DECODER:U1|WideOr2~68 DECODER:U1|WideOr2~65 KEY_BUFFER:U2|N_T[0][0] } { 0.000ns 0.000ns 5.931ns 0.443ns 0.443ns 1.241ns } { 0.000ns 1.475ns 0.590ns 0.292ns 0.292ns 0.478ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { KEY_DOWN KEY_BUFFER:U2|N_T[0][0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { KEY_DOWN KEY_DOWN~out0 KEY_BUFFER:U2|N_T[0][0] } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}