alarm_clock.fnsim.qmsg

本文件是针对了解闹钟控制系统而写的一个VHDL源代码。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 11 13:29:56 2008 " "Info: Processing started: Thu Dec 11 13:29:56 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off alarm_clock -c alarm_clock --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off alarm_clock -c alarm_clock --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alarm_clock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file alarm_clock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ALARM_CLOCK-ART " "Info: Found design unit 1: ALARM_CLOCK-ART" {  } { { "alarm_clock.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/alarm_clock.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ALARM_CLOCK " "Info: Found entity 1: ALARM_CLOCK" {  } { { "alarm_clock.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/alarm_clock.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alarm_controller.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file alarm_controller.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ALARM_CONTROLLER-ART " "Info: Found design unit 1: ALARM_CONTROLLER-ART" {  } { { "alarm_controller.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/alarm_controller.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ALARM_CONTROLLER " "Info: Found entity 1: ALARM_CONTROLLER" {  } { { "alarm_controller.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/alarm_controller.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alarm_counter.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file alarm_counter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ALARM_COUNTER-ART " "Info: Found design unit 1: ALARM_COUNTER-ART" {  } { { "alarm_counter.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/alarm_counter.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ALARM_COUNTER " "Info: Found entity 1: ALARM_COUNTER" {  } { { "alarm_counter.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/alarm_counter.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alarm_reg.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file alarm_reg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ALARM_REG-ART " "Info: Found design unit 1: ALARM_REG-ART" {  } { { "alarm_reg.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/alarm_reg.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ALARM_REG " "Info: Found entity 1: ALARM_REG" {  } { { "alarm_reg.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/alarm_reg.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decoder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file decoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DECODER-ART " "Info: Found design unit 1: DECODER-ART" {  } { { "decoder.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/decoder.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 DECODER " "Info: Found entity 1: DECODER" {  } { { "decoder.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/decoder.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "display_driver.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file display_driver.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DISPLAY_DRIVER-ART " "Info: Found design unit 1: DISPLAY_DRIVER-ART" {  } { { "display_driver.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/display_driver.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 DISPLAY_DRIVER " "Info: Found entity 1: DISPLAY_DRIVER" {  } { { "display_driver.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/display_driver.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fq_divider.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fq_divider.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FQ_DIVIDER-ART " "Info: Found design unit 1: FQ_DIVIDER-ART" {  } { { "fq_divider.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/fq_divider.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 FQ_DIVIDER " "Info: Found entity 1: FQ_DIVIDER" {  } { { "fq_divider.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/fq_divider.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key_buffer.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file key_buffer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 KEY_BUFFER-ART " "Info: Found design unit 1: KEY_BUFFER-ART" {  } { { "key_buffer.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/key_buffer.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 KEY_BUFFER " "Info: Found entity 1: KEY_BUFFER" {  } { { "key_buffer.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/key_buffer.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "p_alarm.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file p_alarm.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 P_ALARM " "Info: Found design unit 1: P_ALARM" {  } { { "p_alarm.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/p_alarm.vhd" 3 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alarmclock.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file alarmclock.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 alarmclock " "Info: Found entity 1: alarmclock" {  } { { "alarmclock.bdf" "" { Schematic "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/alarmclock.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "alarm_clock " "Info: Elaborating entity \"alarm_clock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "DECODER DECODER:U1 A:art " "Info: Elaborating entity \"DECODER\" using architecture \"A:art\" for hierarchy \"DECODER:U1\"" {  } { { "alarm_clock.vhd" "U1" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/alarm_clock.vhd" 82 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "KEY_BUFFER KEY_BUFFER:U2 A:art " "Info: Elaborating entity \"KEY_BUFFER\" using architecture \"A:art\" for hierarchy \"KEY_BUFFER:U2\"" {  } { { "alarm_clock.vhd" "U2" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/alarm_clock.vhd" 83 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "ALARM_CONTROLLER ALARM_CONTROLLER:U3 A:art " "Info: Elaborating entity \"ALARM_CONTROLLER\" using architecture \"A:art\" for hierarchy \"ALARM_CONTROLLER:U3\"" {  } { { "alarm_clock.vhd" "U3" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/alarm_clock.vhd" 84 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "ALARM_COUNTER ALARM_COUNTER:U4 A:art " "Info: Elaborating entity \"ALARM_COUNTER\" using architecture \"A:art\" for hierarchy \"ALARM_COUNTER:U4\"" {  } { { "alarm_clock.vhd" "U4" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/alarm_clock.vhd" 85 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "NEW_CURRENT_TIME alarm_counter.vhd(22) " "Warning (10492): VHDL Process Statement warning at alarm_counter.vhd(22): signal \"NEW_CURRENT_TIME\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "alarm_counter.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/alarm_counter.vhd" 22 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "ALARM_REG ALARM_REG:U5 A:art " "Info: Elaborating entity \"ALARM_REG\" using architecture \"A:art\" for hierarchy \"ALARM_REG:U5\"" {  } { { "alarm_clock.vhd" "U5" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/alarm_clock.vhd" 86 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "DISPLAY_DRIVER DISPLAY_DRIVER:U6 A:art " "Info: Elaborating entity \"DISPLAY_DRIVER\" using architecture \"A:art\" for hierarchy \"DISPLAY_DRIVER:U6\"" {  } { { "alarm_clock.vhd" "U6" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/alarm_clock.vhd" 87 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "DISPLAY_TIME display_driver.vhd(16) " "Warning (10631): VHDL Process Statement warning at display_driver.vhd(16): inferring latch(es) for signal or variable \"DISPLAY_TIME\", which holds its previous value in one or more paths through the process" {  } { { "display_driver.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/display_driver.vhd" 16 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "DISPLAY_TIME\[0\]\[0\] display_driver.vhd(16) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(16): inferred latch for \"DISPLAY_TIME\[0\]\[0\]\"" {  } { { "display_driver.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/display_driver.vhd" 16 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "DISPLAY_TIME\[0\]\[1\] display_driver.vhd(16) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(16): inferred latch for \"DISPLAY_TIME\[0\]\[1\]\"" {  } { { "display_driver.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/display_driver.vhd" 16 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "DISPLAY_TIME\[0\]\[2\] display_driver.vhd(16) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(16): inferred latch for \"DISPLAY_TIME\[0\]\[2\]\"" {  } { { "display_driver.vhd" "" { Text "C:/Documents and Settings/yujiangwang/桌面/12月任务/闹钟控制系统/display_driver.vhd" 16 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}