display_driver.vhd

本文件是针对了解闹钟控制系统而写的一个VHDL源代码。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.P_ALARM.ALL;
ENTITY DISPLAY_DRIVER IS
   PORT(ALARM_TIME :IN  T_CLOCK_TIME;
     CURRENT_TIME :IN  T_CLOCK_TIME;
     NEW_TIME :IN  T_CLOCK_TIME;
     SHOW_NEW_TIME:IN  STD_LOGIC;
     SHOW_A :IN  STD_LOGIC;
     SOUND_ALARM :OUT STD_LOGIC;
     DISPLAY:OUT T_DISPLAY);
END ENTITY DISPLAY_DRIVER;
ARCHITECTURE ART OF DISPLAY_DRIVER IS
   SIGNAL DISPLAY_TIME:T_CLOCK_TIME;
   BEGIN
   CTRL:PROCESS(ALARM_TIME,CURRENT_TIME,NEW_TIME,SHOW_A,SHOW_NEW_TIME)IS
   BEGIN
       SOUND_LP: FOR I IN ALARM_TIME'RANGE LOOP
         IF NOT(ALARM_TIME(I) = CURRENT_TIME(I)) THEN
            SOUND_ALARM <= '0';
            EXIT SOUND_LP;
         ELSE   
            SOUND_ALARM <= '1';
         END IF;
      END LOOP SOUND_LP;
         IF SHOW_NEW_TIME = '1' THEN
         DISPLAY_TIME <= NEW_TIME;
      ELSIF SHOW_A = '1' THEN
         DISPLAY_TIME <= ALARM_TIME;
      ELSIF SHOW_A = '0' THEN
         DISPLAY_TIME <= CURRENT_TIME;
      ELSE
         ASSERT FALSE REPORT "UNCERTAIN DISPLAY_DRIVER CONTROL!" SEVERITY WARNING;
      END IF;
   END PROCESS CTRL;
    DISP:PROCESS(DISPLAY_TIME)IS
   BEGIN
      FOR I IN DISPLAY_TIME'RANGE LOOP
         DISPLAY(I) <= SEVEN_SEG(DISPLAY_TIME(I));
      END LOOP;
   END PROCESS DISP;     
END ARCHITECTURE ART;