alarm_clock.tan.rpt

本文件是针对了解闹钟控制系统而写的一个VHDL源代码。

+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Minimum tpd to report                                 ; 0 ns               ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; Off                ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; KEY_DOWN        ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'KEY_DOWN'                                                                                                                                                                                                ;
+-------+------------------------------------------------+-------------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                    ; To                      ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; KEY_BUFFER:U2|N_T[0][1] ; KEY_BUFFER:U2|N_T[1][1] ; KEY_DOWN   ; KEY_DOWN ; None                        ; None                      ; 0.695 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; KEY_BUFFER:U2|N_T[0][2] ; KEY_BUFFER:U2|N_T[1][2] ; KEY_DOWN   ; KEY_DOWN ; None                        ; None                      ; 0.695 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; KEY_BUFFER:U2|N_T[0][3] ; KEY_BUFFER:U2|N_T[1][3] ; KEY_DOWN   ; KEY_DOWN ; None                        ; None                      ; 0.694 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; KEY_BUFFER:U2|N_T[2][1] ; KEY_BUFFER:U2|N_T[3][1] ; KEY_DOWN   ; KEY_DOWN ; None                        ; None                      ; 0.693 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; KEY_BUFFER:U2|N_T[1][1] ; KEY_BUFFER:U2|N_T[2][1] ; KEY_DOWN   ; KEY_DOWN ; None                        ; None                      ; 0.690 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; KEY_BUFFER:U2|N_T[0][0] ; KEY_BUFFER:U2|N_T[1][0] ; KEY_DOWN   ; KEY_DOWN ; None                        ; None                      ; 0.687 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; KEY_BUFFER:U2|N_T[2][3] ; KEY_BUFFER:U2|N_T[3][3] ; KEY_DOWN   ; KEY_DOWN ; None                        ; None                      ; 0.687 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; KEY_BUFFER:U2|N_T[1][2] ; KEY_BUFFER:U2|N_T[2][2] ; KEY_DOWN   ; KEY_DOWN ; None                        ; None                      ; 0.685 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; KEY_BUFFER:U2|N_T[2][2] ; KEY_BUFFER:U2|N_T[3][2] ; KEY_DOWN   ; KEY_DOWN ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; KEY_BUFFER:U2|N_T[1][0] ; KEY_BUFFER:U2|N_T[2][0] ; KEY_DOWN   ; KEY_DOWN ; None                        ; None                      ; 0.679 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; KEY_BUFFER:U2|N_T[1][3] ; KEY_BUFFER:U2|N_T[2][3] ; KEY_DOWN   ; KEY_DOWN ; None                        ; None                      ; 0.677 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; KEY_BUFFER:U2|N_T[2][0] ; KEY_BUFFER:U2|N_T[3][0] ; KEY_DOWN   ; KEY_DOWN ; None                        ; None                      ; 0.665 ns                ;
+-------+------------------------------------------------+-------------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                        ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------+---------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                  ; To                                    ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------+---------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 176.09 MHz ( period = 5.679 ns )                    ; FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[0]      ; FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[7]      ; CLK        ; CLK      ; None                        ; None                      ; 5.418 ns                ;
; N/A                                     ; 176.09 MHz ( period = 5.679 ns )                    ; FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[0]      ; FQ_DIVIDER:U7|\DIVIDE_CLK:CNT[3]      ; CLK        ; CLK      ; None                        ; None                      ; 5.418 ns                ;