alarm_reg.vhd

本文件是针对了解闹钟控制系统而写的一个VHDL源代码。

--闹钟寄存器的源程序ALARM_REG.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.P_ALARM.ALL;
ENTITY ALARM_REG IS
   PORT(NEW_ALARM_TIME:IN  T_CLOCK_TIME;
         LOAD_NEW_A :IN  STD_LOGIC;
         CLK :IN  STD_LOGIC;
RESET :IN  STD_LOGIC;
      ALARM_TIME    :OUT T_CLOCK_TIME);
END ENTITY ALARM_REG;
ARCHITECTURE ART OF ALARM_REG IS
   BEGIN
   PROCESS(CLK,RESET)
   BEGIN
      IF RESET = '1' THEN
         ALARM_TIME <= (0,0,0,0);
      ELSE
         IF RISING_EDGE(CLK) THEN
            IF LOAD_NEW_A = '1' THEN
               ALARM_TIME <= NEW_ALARM_TIME;
ELSIF LOAD_NEW_A /= '0' THEN
                    ASSERT FALSE REPORT"UNCERTAIN LOAD_NEW_ALARM CONTROL!"
                     SEVERITY WARNING;
            END IF;
         END IF;
      END IF;
   END PROCESS;
END ARCHITECTURE ART;