mips_top.map.qmsg

是verilog做的简化mips32指令系统。 有些小问题

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_7201 Ifetch32:ifetch\|lpm_rom:prgrom\|altrom:srom\|altsyncram:rom_block\|altsyncram_7201:auto_generated " "Info: Elaborating entity \"altsyncram_7201\" for hierarchy \"Ifetch32:ifetch\|lpm_rom:prgrom\|altrom:srom\|altsyncram:rom_block\|altsyncram_7201:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Registers32 Registers32:registers " "Info: Elaborating entity \"Registers32\" for hierarchy \"Registers32:registers\"" {  } { { "Mips_Top.v" "registers" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.v" 56 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Controler Controler:controler " "Info: Elaborating entity \"Controler\" for hierarchy \"Controler:controler\"" {  } { { "Mips_Top.v" "controler" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.v" 73 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ALUDecoder ALUDecoder:aludecoder " "Info: Elaborating entity \"ALUDecoder\" for hierarchy \"ALUDecoder:aludecoder\"" {  } { { "Mips_Top.v" "aludecoder" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.v" 78 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SignExt32 SignExt32:signext " "Info: Elaborating entity \"SignExt32\" for hierarchy \"SignExt32:signext\"" {  } { { "Mips_Top.v" "signext" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.v" 83 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ALU32 ALU32:alu " "Info: Elaborating entity \"ALU32\" for hierarchy \"ALU32:alu\"" {  } { { "Mips_Top.v" "alu" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.v" 94 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "r1 ALU32.v(33) " "Warning (10235): Verilog HDL Always Construct warning at ALU32.v(33): variable \"r1\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 33 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "ALUSrc ALU32.v(35) " "Warning (10235): Verilog HDL Always Construct warning at ALU32.v(35): variable \"ALUSrc\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 35 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "im ALU32.v(37) " "Warning (10235): Verilog HDL Always Construct warning at ALU32.v(37): variable \"im\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 37 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "r2 ALU32.v(41) " "Warning (10235): Verilog HDL Always Construct warning at ALU32.v(41): variable \"r2\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 41 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "aluctrl ALU32.v(44) " "Warning (10235): Verilog HDL Always Construct warning at ALU32.v(44): variable \"aluctrl\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 44 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "result_addtemp ALU32.v(51) " "Warning (10235): Verilog HDL Always Construct warning at ALU32.v(51): variable \"result_addtemp\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 51 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_IGNORED_SYSTEM_TASK" "ALU32.v(54) " "Warning (10175): Verilog HDL warning at ALU32.v(54): ignoring unsupported system task" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 54 0 0 } }  } 0 10175 "Verilog HDL warning at %1!s!: ignoring unsupported system task" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "result_addtemp ALU32.v(60) " "Warning (10235): Verilog HDL Always Construct warning at ALU32.v(60): variable \"result_addtemp\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 60 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_IGNORED_SYSTEM_TASK" "ALU32.v(63) " "Warning (10175): Verilog HDL warning at ALU32.v(63): ignoring unsupported system task" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 63 0 0 } }  } 0 10175 "Verilog HDL warning at %1!s!: ignoring unsupported system task" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "result_addtemp ALU32.v(68) " "Warning (10235): Verilog HDL Always Construct warning at ALU32.v(68): variable \"result_addtemp\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 68 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_IGNORED_SYSTEM_TASK" "ALU32.v(71) " "Warning (10175): Verilog HDL warning at ALU32.v(71): ignoring unsupported system task" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 71 0 0 } }  } 0 10175 "Verilog HDL warning at %1!s!: ignoring unsupported system task" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "result_addtemp ALU32.v(76) " "Warning (10235): Verilog HDL Always Construct warning at ALU32.v(76): variable \"result_addtemp\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 76 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_IGNORED_SYSTEM_TASK" "ALU32.v(79) " "Warning (10175): Verilog HDL warning at ALU32.v(79): ignoring unsupported system task" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 79 0 0 } }  } 0 10175 "Verilog HDL warning at %1!s!: ignoring unsupported system task" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "result_shifttemp ALU32.v(85) " "Warning (10235): Verilog HDL Always Construct warning at ALU32.v(85): variable \"result_shifttemp\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 85 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_IGNORED_SYSTEM_TASK" "ALU32.v(88) " "Warning (10175): Verilog HDL warning at ALU32.v(88): ignoring unsupported system task" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 88 0 0 } }  } 0 10175 "Verilog HDL warning at %1!s!: ignoring unsupported system task" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "result_shifttemp ALU32.v(94) " "Warning (10235): Verilog HDL Always Construct warning at ALU32.v(94): variable \"result_shifttemp\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 94 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_IGNORED_SYSTEM_TASK" "ALU32.v(97) " "Warning (10175): Verilog HDL warning at ALU32.v(97): ignoring unsupported system task" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 97 0 0 } }  } 0 10175 "Verilog HDL warning at %1!s!: ignoring unsupported system task" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "result ALU32.v(29) " "Warning (10240): Verilog HDL Always Construct warning at ALU32.v(29): inferring latch(es) for variable \"result\", which holds its previous value in one or more paths through the always construct" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "s1 ALU32.v(29) " "Warning (10240): Verilog HDL Always Construct warning at ALU32.v(29): inferring latch(es) for variable \"s1\", which holds its previous value in one or more paths through the always construct" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "s2 ALU32.v(29) " "Warning (10240): Verilog HDL Always Construct warning at ALU32.v(29): inferring latch(es) for variable \"s2\", which holds its previous value in one or more paths through the always construct" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "signal ALU32.v(29) " "Warning (10240): Verilog HDL Always Construct warning at ALU32.v(29): inferring latch(es) for variable \"signal\", which holds its previous value in one or more paths through the always construct" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "a1 ALU32.v(29) " "Warning (10240): Verilog HDL Always Construct warning at ALU32.v(29): inferring latch(es) for variable \"a1\", which holds its previous value in one or more paths through the always construct" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "a2 ALU32.v(29) " "Warning (10240): Verilog HDL Always Construct warning at ALU32.v(29): inferring latch(es) for variable \"a2\", which holds its previous value in one or more paths through the always construct" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "zero ALU32.v(29) " "Warning (10240): Verilog HDL Always Construct warning at ALU32.v(29): inferring latch(es) for variable \"zero\", which holds its previous value in one or more paths through the always construct" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "zero ALU32.v(29) " "Info (10041): Inferred latch for \"zero\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[0\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[0\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[1\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[1\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[2\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[2\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[3\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[3\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}