mips_top.map.qmsg

来自「是verilog做的简化mips32指令系统。 有些小问题」· QMSG 代码 · 共 175 行 · 第 1/5 页

{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[4\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[4\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[5\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[5\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[6\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[6\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[7\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[7\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[8\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[8\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[9\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[9\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[10\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[10\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[11\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[11\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[12\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[12\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[13\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[13\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[14\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[14\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[15\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[15\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[16\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[16\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[17\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[17\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[18\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[18\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[19\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[19\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[20\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[20\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[21\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[21\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[22\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[22\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[23\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[23\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[24\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[24\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[25\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[25\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[26\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[26\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[27\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[27\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[28\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[28\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[29\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[29\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[30\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[30\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a2\[31\] ALU32.v(29) " "Info (10041): Inferred latch for \"a2\[31\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a1\[0\] ALU32.v(29) " "Info (10041): Inferred latch for \"a1\[0\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a1\[1\] ALU32.v(29) " "Info (10041): Inferred latch for \"a1\[1\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a1\[2\] ALU32.v(29) " "Info (10041): Inferred latch for \"a1\[2\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a1\[3\] ALU32.v(29) " "Info (10041): Inferred latch for \"a1\[3\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a1\[4\] ALU32.v(29) " "Info (10041): Inferred latch for \"a1\[4\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a1\[5\] ALU32.v(29) " "Info (10041): Inferred latch for \"a1\[5\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "a1\[6\] ALU32.v(29) " "Info (10041): Inferred latch for \"a1\[6\]\" at ALU32.v(29)" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 29 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}