mips_top.map.qmsg

是verilog做的简化mips32指令系统。 有些小问题

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 17 23:24:14 2008 " "Info: Processing started: Wed Dec 17 23:24:14 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Mips_Top -c Mips_Top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Mips_Top -c Mips_Top" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "clock_gen.v(13) " "Warning (10268): Verilog HDL information at clock_gen.v(13): Always Construct contains both blocking and non-blocking assignments" {  } { { "clock_gen.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/clock_gen.v" 13 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock_gen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clock_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock_gen " "Info: Found entity 1: clock_gen" {  } { { "clock_gen.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/clock_gen.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add32.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file add32.v" { { "Info" "ISGN_ENTITY_NAME" "1 add32 " "Info: Found entity 1: add32" {  } { { "add32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/add32.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALU32.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ALU32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ALU32 " "Info: Found entity 1: ALU32" {  } { { "ALU32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALU32.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALUDecoder.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ALUDecoder.v" { { "Info" "ISGN_ENTITY_NAME" "1 ALUDecoder " "Info: Found entity 1: ALUDecoder" {  } { { "ALUDecoder.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/ALUDecoder.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Controler.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Controler.v" { { "Info" "ISGN_ENTITY_NAME" "1 Controler " "Info: Found entity 1: Controler" {  } { { "Controler.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Controler.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Dmemory32.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Dmemory32.v" { { "Info" "ISGN_ENTITY_NAME" "1 Dmemory32 " "Info: Found entity 1: Dmemory32" {  } { { "Dmemory32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Dmemory32.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "Ifetch32.v(29) " "Warning (10268): Verilog HDL information at Ifetch32.v(29): Always Construct contains both blocking and non-blocking assignments" {  } { { "Ifetch32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Ifetch32.v" 29 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Ifetch32.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Ifetch32.v" { { "Info" "ISGN_ENTITY_NAME" "1 Ifetch32 " "Info: Found entity 1: Ifetch32" {  } { { "Ifetch32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Ifetch32.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Registers32.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Registers32.v" { { "Info" "ISGN_ENTITY_NAME" "1 Registers32 " "Info: Found entity 1: Registers32" {  } { { "Registers32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Registers32.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter32_var.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter32_var.v" { { "Info" "ISGN_ENTITY_NAME" "1 shifter32_var " "Info: Found entity 1: shifter32_var" {  } { { "shifter32_var.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/shifter32_var.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SignExt32.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SignExt32.v" { { "Info" "ISGN_ENTITY_NAME" "1 SignExt32 " "Info: Found entity 1: SignExt32" {  } { { "SignExt32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/SignExt32.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_INGORE_DANGLING_COMMA" "Mips_Top.v(42) " "Warning (10275): Verilog HDL Module Instantiation warning at Mips_Top.v(42): ignored dangling comma in List of Port Connections" {  } { { "Mips_Top.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.v" 42 0 0 } }  } 0 10275 "Verilog HDL Module Instantiation warning at %1!s!: ignored dangling comma in List of Port Connections" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_INGORE_DANGLING_COMMA" "Mips_Top.v(83) " "Warning (10275): Verilog HDL Module Instantiation warning at Mips_Top.v(83): ignored dangling comma in List of Port Connections" {  } { { "Mips_Top.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.v" 83 0 0 } }  } 0 10275 "Verilog HDL Module Instantiation warning at %1!s!: ignored dangling comma in List of Port Connections" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "rwds Mips_Top.v(53) " "Warning (10236): Verilog HDL Implicit Net warning at Mips_Top.v(53): created implicit net for \"rwds\"" {  } { { "Mips_Top.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.v" 53 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Mips_Top.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Mips_Top.v" { { "Info" "ISGN_ENTITY_NAME" "1 Mips_Top " "Info: Found entity 1: Mips_Top" {  } { { "Mips_Top.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Mips_Top " "Info: Elaborating entity \"Mips_Top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_gen clock_gen:clocks " "Info: Elaborating entity \"clock_gen\" for hierarchy \"clock_gen:clocks\"" {  } { { "Mips_Top.v" "clocks" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.v" 29 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Ifetch32 Ifetch32:ifetch " "Info: Elaborating entity \"Ifetch32\" for hierarchy \"Ifetch32:ifetch\"" {  } { { "Mips_Top.v" "ifetch" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.v" 42 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/lpm_rom.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/lpm_rom.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom " "Info: Found entity 1: lpm_rom" {  } { { "lpm_rom.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_rom.tdf" 43 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom Ifetch32:ifetch\|lpm_rom:prgrom " "Info: Elaborating entity \"lpm_rom\" for hierarchy \"Ifetch32:ifetch\|lpm_rom:prgrom\"" {  } { { "Ifetch32.v" "prgrom" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Ifetch32.v" 21 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "Ifetch32:ifetch\|lpm_rom:prgrom " "Info: Elaborated megafunction instantiation \"Ifetch32:ifetch\|lpm_rom:prgrom\"" {  } { { "Ifetch32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Ifetch32.v" 21 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/altrom.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/altrom.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altrom " "Info: Found entity 1: altrom" {  } { { "altrom.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/altrom.tdf" 77 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom Ifetch32:ifetch\|lpm_rom:prgrom\|altrom:srom " "Info: Elaborating entity \"altrom\" for hierarchy \"Ifetch32:ifetch\|lpm_rom:prgrom\|altrom:srom\"" {  } { { "lpm_rom.tdf" "srom" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_rom.tdf" 54 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WTDFX_ASSERTION" "altrom does not support Stratix II device family -- attempting best-case memory conversions, but power-up states will be different for Stratix II devices " "Warning: Assertion warning: altrom does not support Stratix II device family -- attempting best-case memory conversions, but power-up states will be different for Stratix II devices" {  } { { "altrom.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/altrom.tdf" 175 2 0 } } { "lpm_rom.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_rom.tdf" 54 3 0 } } { "Ifetch32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Ifetch32.v" 21 0 0 } } { "Mips_Top.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Mips_Top.v" 37 0 0 } }  } 0 0 "Assertion warning: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "Ifetch32:ifetch\|lpm_rom:prgrom\|altrom:srom Ifetch32:ifetch\|lpm_rom:prgrom " "Info: Elaborated megafunction instantiation \"Ifetch32:ifetch\|lpm_rom:prgrom\|altrom:srom\", which is child of megafunction instantiation \"Ifetch32:ifetch\|lpm_rom:prgrom\"" {  } { { "lpm_rom.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_rom.tdf" 54 3 0 } } { "Ifetch32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Ifetch32.v" 21 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Ifetch32:ifetch\|lpm_rom:prgrom " "Info: Instantiated megafunction \"Ifetch32:ifetch\|lpm_rom:prgrom\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 32 " "Info: Parameter \"lpm_width\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthad 10 " "Info: Parameter \"lpm_widthad\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_file mips32.mif " "Info: Parameter \"lpm_file\" = \"mips32.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_outdata REGISTERED " "Info: Parameter \"lpm_outdata\" = \"REGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_address_control REGISTERED " "Info: Parameter \"lpm_address_control\" = \"REGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "Ifetch32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Ifetch32.v" 21 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram Ifetch32:ifetch\|lpm_rom:prgrom\|altrom:srom\|altsyncram:rom_block " "Info: Elaborating entity \"altsyncram\" for hierarchy \"Ifetch32:ifetch\|lpm_rom:prgrom\|altrom:srom\|altsyncram:rom_block\"" {  } { { "altrom.tdf" "rom_block" { Text "e:/altera/72/quartus/libraries/megafunctions/altrom.tdf" 90 7 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "Ifetch32:ifetch\|lpm_rom:prgrom\|altrom:srom\|altsyncram:rom_block Ifetch32:ifetch\|lpm_rom:prgrom " "Info: Elaborated megafunction instantiation \"Ifetch32:ifetch\|lpm_rom:prgrom\|altrom:srom\|altsyncram:rom_block\", which is child of megafunction instantiation \"Ifetch32:ifetch\|lpm_rom:prgrom\"" {  } { { "altrom.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/altrom.tdf" 90 7 0 } } { "Ifetch32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Ifetch32.v" 21 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "Ifetch32:ifetch\|lpm_rom:prgrom " "Info: Instantiated megafunction \"Ifetch32:ifetch\|lpm_rom:prgrom\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 32 " "Info: Parameter \"lpm_width\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthad 10 " "Info: Parameter \"lpm_widthad\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_file mips32.mif " "Info: Parameter \"lpm_file\" = \"mips32.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_outdata REGISTERED " "Info: Parameter \"lpm_outdata\" = \"REGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_address_control REGISTERED " "Info: Parameter \"lpm_address_control\" = \"REGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "Ifetch32.v" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/Ifetch32.v" 21 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_7201.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_7201.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_7201 " "Info: Found entity 1: altsyncram_7201" {  } { { "db/altsyncram_7201.tdf" "" { Text "D:/My Documents/Courses/ComputerOrganizationAndDesign_E/Mips_Top/db/altsyncram_7201.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}