t_fir.v

基于verilog的fir滤波器设计

`define auto_init
`timescale 1ns/1ns
`define INPUT_FILE "c.bin"
`define OUTPUT_FILE "c_o.bin"

module t_fir();
	
	parameter NOOFDATA = 4000,	// NO. of data
			  IDATA_WIDTH = 8,	// input data width
			  PDATA_WIDTH =17,	// process data width
			  FIR_TAP = 11,		// fir tap
			  FIR_TAPHALF = 6,	// fir tap half
			  COEFF_WIDTH = 7,	// coff width
			  OUT_WIDTH = 28;	// output width
	
	parameter CLK_CYCLE = 20,
			  CLK_HCYCLE = 10;	// half clock cycle
	
	// input
	reg clk;
	reg rst_n;
	reg [2*IDATA_WIDTH - 1:0] fir_in;
	
	// output
	wire [OUT_WIDTH - 1:0] fir_out;
	
	// reg
	integer regcount,cnt;
	reg [IDATA_WIDTH - 1:0] memb [NOOFDATA - 1:0];	// memory used for storing
												// input file data(binary)
	reg [OUT_WIDTH - 1:0] membyte [NOOFDATA - 1:0]; // for storing output
	reg write_able;		// write data to file signal
	integer count; 	// write data count signal
	integer handle;	// file handle
	
	// 
	reg [2:0] state_wr;
	integer cnt1;
	
	// ins
	fir_parall_v1 dut(
		.clk(clk),
		.rst_n(rst_n),
		.fir_in(fir_in),
		.fir_out(fir_out)
	);
	
	
	// Initialize Inputs
	// Read the data in file into memory
	`ifdef auto_init
		initial
		begin
			// NOTE:THE DATA INPUT FILES MUST EXIST
			$readmemb(`INPUT_FILE, memb);
			regcount = 0;
			count = 0;
			handle = 0;
			clk = 1'b0;
			rst_n = 1'b0;
			#(2*CLK_CYCLE) rst_n = 1'b1;
			#(3000*CLK_CYCLE) $stop;
		end
	`endif
	
	always #CLK_HCYCLE clk = ~clk;	// generate clock signal
	
	always @(posedge clk or negedge rst_n)
	begin
		if (!rst_n) begin
			regcount = 0;
			cnt <= 0;
			fir_in <= 16'b0;
			write_able <= 1'b0;
		end
		else begin
		   //$display("%h",memb[regcount]);
			regcount = regcount + 2;
			fir_in[7:0] <= memb[regcount];		// input testcase
			fir_in[15:8] <= memb[regcount + 1];
			if (regcount > 'd10) begin   // fir_out?fir_in??10?clk???
			   membyte[cnt] <= fir_out;	// output data into memory
			   cnt <= cnt + 1;
			   write_able <= 1'b1;	
			end
		end
	end
	
	/*always @(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			write <= 1'b0;
		else if (regcount == NOOFDATA)
			write <= 1'b1;					// generate write file signal
	end*/
	
	
	// On reaching the end of the file, store the output data memory into file
	always @(posedge clk or negedge rst_n)
	begin
		if (!rst_n) begin
			state_wr <= 'b001;
			cnt1 <= 0;
		end
		else
		case(state_wr)
 'b001: begin
         handle = $fopen(`OUTPUT_FILE);
         $fdisplay(handle,"@%b",000);
         state_wr <= 'b010;
       end
 'b010: if (cnt1 >= 'd1000) // ??fir_out???
           $fclose(handle);
        else
        if (write_able) begin
           $fdisplay(handle,"%b%b%b%b%b%b%b%b ",
           fir_out[7],fir_out[6],fir_out[5],fir_out[4],
           fir_out[3],fir_out[2],fir_out[1],fir_out[0]);
           $fdisplay(handle,"%b%b%b%b%b%b%b%b ",
           fir_out[15],fir_out[14],fir_out[13],fir_out[12],
           fir_out[11],fir_out[10],fir_out[9],fir_out[8]);
           $fdisplay(handle,"%b%b%b%b%b%b%b%b ",
           fir_out[23],fir_out[22],fir_out[21],fir_out[20],
           fir_out[19],fir_out[18],fir_out[17],fir_out[16]);
           $fdisplay(handle,"%b%b%b%b%b%b%b%b ",
           fir_out[27],fir_out[27],fir_out[27],fir_out[27],
           fir_out[27],fir_out[26],fir_out[25],fir_out[24]);
           cnt1 <= cnt1 + 'b1;
        end
  default: state_wr <= 3'bxxx;     
    endcase
   end
	
endmodule