watch.rpt

2个按键的跑表

-- Node name is '|LPM_ADD_SUB:472|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C19', type is buried 
!_LC3_C19 = _LC3_C19~NOT;
_LC3_C19~NOT = LCELL( _EQ040);
  _EQ040 = !sec_111
         # !sec_110;

-- Node name is '|LPM_ADD_SUB:531|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C21', type is buried 
!_LC2_C21 = _LC2_C21~NOT;
_LC2_C21~NOT = LCELL( _EQ041);
  _EQ041 = !min_001
         # !min_000;

-- Node name is '|LPM_ADD_SUB:590|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C24', type is buried 
!_LC2_C24 = _LC2_C24~NOT;
_LC2_C24~NOT = LCELL( _EQ042);
  _EQ042 = !min_111
         # !min_110;

-- Node name is ':308' 
-- Equation name is '_LC6_C15', type is buried 
_LC6_C15 = LCELL( _EQ043);
  _EQ043 =  mic_000 & !mic_001 & !mic_002 &  mic_003;

-- Node name is ':367' 
-- Equation name is '_LC1_C7', type is buried 
_LC1_C7  = LCELL( _EQ044);
  _EQ044 =  mic_110 & !mic_111 & !mic_112 &  mic_113;

-- Node name is ':426' 
-- Equation name is '_LC2_C13', type is buried 
_LC2_C13 = LCELL( _EQ045);
  _EQ045 =  sec_000 & !sec_001 & !sec_002 &  sec_003;

-- Node name is ':485' 
-- Equation name is '_LC1_C19', type is buried 
_LC1_C19 = LCELL( _EQ046);
  _EQ046 =  sec_110 & !sec_111 &  sec_112 & !sec_113;

-- Node name is ':544' 
-- Equation name is '_LC1_C21', type is buried 
_LC1_C21 = LCELL( _EQ047);
  _EQ047 =  min_000 & !min_001 & !min_002 &  min_003;

-- Node name is '~603~1' 
-- Equation name is '~603~1', location is LC2_C22, type is buried.
-- synthesized logic cell 
_LC2_C22 = LCELL( _EQ048);
  _EQ048 =  min_111
         # !min_110;

-- Node name is '~704~1' 
-- Equation name is '~704~1', location is LC1_C24, type is buried.
-- synthesized logic cell 
_LC1_C24 = LCELL( _EQ049);
  _EQ049 =  _LC1_C21 &  min_113
         #  _LC1_C21 & !min_112
         #  _LC1_C21 &  _LC2_C22;

-- Node name is '~770~1' 
-- Equation name is '~770~1', location is LC6_C21, type is buried.
-- synthesized logic cell 
_LC6_C21 = LCELL( _EQ050);
  _EQ050 =  _LC1_C19 & !_LC1_C21;

-- Node name is '~864~1' 
-- Equation name is '~864~1', location is LC3_C17, type is buried.
-- synthesized logic cell 
_LC3_C17 = LCELL( _EQ051);
  _EQ051 = !_LC1_C19 &  _LC2_C13;

-- Node name is ':985' 
-- Equation name is '_LC3_C13', type is buried 
_LC3_C13 = LCELL( _EQ052);
  _EQ052 =  _LC1_C7 & !_LC2_C13 &  _LC7_C13
         # !_LC1_C7 &  sec_003;

-- Node name is '~1136~1' 
-- Equation name is '~1136~1', location is LC5_C7, type is buried.
-- synthesized logic cell 
_LC5_C7  = LCELL( _EQ053);
  _EQ053 = !_LC1_C7 &  _LC6_C15;

-- Node name is ':1136' 
-- Equation name is '_LC2_C7', type is buried 
_LC2_C7  = LCELL( _EQ054);
  _EQ054 =  _LC5_C7 & !_LC7_C7 &  mic_113
         #  _LC5_C7 & !mic_112 &  mic_113
         #  _LC5_C7 &  _LC7_C7 &  mic_112 & !mic_113;

-- Node name is ':1142' 
-- Equation name is '_LC3_C7', type is buried 
_LC3_C7  = LCELL( _EQ055);
  _EQ055 =  _LC5_C7 & !mic_111 &  mic_112
         #  _LC5_C7 & !mic_110 &  mic_112
         #  _LC5_C7 &  mic_110 &  mic_111 & !mic_112;

-- Node name is ':1148' 
-- Equation name is '_LC6_C7', type is buried 
_LC6_C7  = LCELL( _EQ056);
  _EQ056 =  _LC5_C7 & !mic_110 &  mic_111
         #  _LC5_C7 &  mic_110 & !mic_111;

-- Node name is '~1345~1' 
-- Equation name is '~1345~1', location is LC1_C13, type is buried.
-- synthesized logic cell 
_LC1_C13 = LCELL( _EQ057);
  _EQ057 =  _LC1_C7 & !_LC2_C13 & !sec_000
         #  _LC8_C10;

-- Node name is '~1351~1' 
-- Equation name is '~1351~1', location is LC8_C10, type is buried.
-- synthesized logic cell 
!_LC8_C10 = _LC8_C10~NOT;
_LC8_C10~NOT = LCELL( _EQ058);
  _EQ058 =  _LC1_C7 &  _LC6_C15 &  start;

-- Node name is '~1357~1' 
-- Equation name is '~1357~1', location is LC6_C19, type is buried.
-- synthesized logic cell 
_LC6_C19 = LCELL( _EQ059);
  _EQ059 =  _LC3_C17 & !sec_112
         #  _LC3_C17 & !_LC3_C19
         #  _LC8_C17;

-- Node name is '~1369~1' 
-- Equation name is '~1369~1', location is LC5_C17, type is buried.
-- synthesized logic cell 
_LC5_C17 = LCELL( _EQ060);
  _EQ060 =  _LC3_C17 & !sec_110
         #  _LC8_C17;

-- Node name is '~1375~1' 
-- Equation name is '~1375~1', location is LC8_C17, type is buried.
-- synthesized logic cell 
!_LC8_C17 = _LC8_C17~NOT;
_LC8_C17~NOT = LCELL( _EQ061);
  _EQ061 =  _LC2_C13 & !_LC8_C10;

-- Node name is '~1381~1' 
-- Equation name is '~1381~1', location is LC8_C21, type is buried.
-- synthesized logic cell 
_LC8_C21 = LCELL( _EQ062);
  _EQ062 =  _LC6_C21 & !min_002
         # !_LC2_C21 &  _LC6_C21
         #  _LC2_C17;

-- Node name is '~1393~1' 
-- Equation name is '~1393~1', location is LC8_C22, type is buried.
-- synthesized logic cell 
_LC8_C22 = LCELL( _EQ063);
  _EQ063 =  _LC6_C21 & !min_000
         #  _LC2_C17;

-- Node name is '~1399~1' 
-- Equation name is '~1399~1', location is LC2_C17, type is buried.
-- synthesized logic cell 
!_LC2_C17 = _LC2_C17~NOT;
_LC2_C17~NOT = LCELL( _EQ064);
  _EQ064 =  _LC1_C19 & !_LC8_C17;

-- Node name is '~1405~1' 
-- Equation name is '~1405~1', location is LC7_C24, type is buried.
-- synthesized logic cell 
_LC7_C24 = LCELL( _EQ065);
  _EQ065 =  _LC1_C24 & !min_112
         #  _LC1_C24 & !_LC2_C24
         #  _LC5_C24;

-- Node name is '~1417~1' 
-- Equation name is '~1417~1', location is LC4_C22, type is buried.
-- synthesized logic cell 
_LC4_C22 = LCELL( _EQ066);
  _EQ066 =  _LC1_C24 & !min_110 &  min_111
         #  _LC5_C24 &  min_111;

-- Node name is '~1423~1' 
-- Equation name is '~1423~1', location is LC5_C24, type is buried.
-- synthesized logic cell 
!_LC5_C24 = _LC5_C24~NOT;
_LC5_C24~NOT = LCELL( _EQ067);
  _EQ067 =  _LC1_C21 & !_LC2_C17;



Project Information                                           d:\yh1\watch.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 17,309K