📄 watch.rpt
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Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\yh1\watch.rpt
watch
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
27 - - C -- OUTPUT 0 1 0 0 mic_00
28 - - C -- OUTPUT 0 1 0 0 mic_01
29 - - C -- OUTPUT 0 1 0 0 mic_02
30 - - C -- OUTPUT 0 1 0 0 mic_03
35 - - - 06 OUTPUT 0 1 0 0 mic_10
36 - - - 07 OUTPUT 0 1 0 0 mic_11
37 - - - 09 OUTPUT 0 1 0 0 mic_12
38 - - - 10 OUTPUT 0 1 0 0 mic_13
54 - - - 21 OUTPUT 0 1 0 0 min_00
58 - - C -- OUTPUT 0 1 0 0 min_01
59 - - C -- OUTPUT 0 1 0 0 min_02
60 - - C -- OUTPUT 0 1 0 0 min_03
61 - - C -- OUTPUT 0 1 0 0 min_10
62 - - C -- OUTPUT 0 1 0 0 min_11
64 - - B -- OUTPUT 0 1 0 0 min_12
65 - - B -- OUTPUT 0 1 0 0 min_13
39 - - - 11 OUTPUT 0 1 0 0 sec_00
47 - - - 14 OUTPUT 0 1 0 0 sec_01
48 - - - 15 OUTPUT 0 1 0 0 sec_02
49 - - - 16 OUTPUT 0 1 0 0 sec_03
50 - - - 17 OUTPUT 0 1 0 0 sec_10
51 - - - 18 OUTPUT 0 1 0 0 sec_11
52 - - - 19 OUTPUT 0 1 0 0 sec_12
53 - - - 20 OUTPUT 0 1 0 0 sec_13
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\yh1\watch.rpt
watch
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - C 15 AND2 0 3 0 1 |LPM_ADD_SUB:295|addcore:adder|:59
- 2 - C 15 OR2 0 3 0 1 |LPM_ADD_SUB:295|addcore:adder|:68
- 7 - C 07 AND2 0 2 0 1 |LPM_ADD_SUB:354|addcore:adder|:55
- 7 - C 13 OR2 0 4 0 1 |LPM_ADD_SUB:413|addcore:adder|:69
- 3 - C 19 OR2 ! 0 2 0 3 |LPM_ADD_SUB:472|addcore:adder|:55
- 2 - C 21 OR2 ! 0 2 0 3 |LPM_ADD_SUB:531|addcore:adder|:55
- 2 - C 24 OR2 ! 0 2 0 3 |LPM_ADD_SUB:590|addcore:adder|:55
- 3 - C 24 AND2 s 0 3 0 2 start~1
- 4 - C 24 AND2 s 0 2 0 1 start~2
- 5 - C 22 AND2 s 0 2 0 1 start~3
- 3 - C 21 AND2 s 0 3 0 2 start~4
- 7 - C 21 AND2 s 0 2 0 1 start~5
- 4 - C 17 AND2 s 0 2 0 1 start~6
- 4 - C 19 AND2 s 0 3 0 2 start~7
- 5 - C 19 AND2 s 0 2 0 1 start~8
- 5 - C 13 AND2 s 1 3 0 2 start~9
- 6 - C 13 OR2 s 0 4 0 1 start~10
- 4 - C 13 AND2 s 0 4 0 1 start~11
- 7 - C 15 DFFE + 2 2 1 1 mic_003 (:28)
- 5 - C 15 DFFE + 2 2 1 3 mic_002 (:29)
- 3 - C 15 DFFE + 2 2 1 3 mic_001 (:30)
- 1 - C 15 DFFE + 2 0 1 4 mic_000 (:31)
- 1 - C 10 DFFE + 2 2 1 2 mic_113 (:32)
- 4 - C 10 DFFE + 2 2 1 3 mic_112 (:33)
- 4 - C 07 DFFE + 2 2 1 4 mic_111 (:34)
- 5 - C 05 DFFE + 2 1 1 4 mic_110 (:35)
- 4 - C 15 DFFE + 2 2 1 3 sec_003 (:36)
- 3 - C 16 DFFE + 1 3 1 3 sec_002 (:37)
- 8 - C 13 DFFE + 1 3 1 4 sec_001 (:38)
- 4 - C 12 DFFE + 1 1 1 6 sec_000 (:39)
- 2 - C 19 DFFE + 1 3 1 1 sec_113 (:40)
- 8 - C 19 DFFE + 1 3 1 3 sec_112 (:41)
- 6 - C 17 DFFE + 1 3 1 2 sec_111 (:42)
- 1 - C 17 DFFE + 1 1 1 4 sec_110 (:43)
- 4 - C 21 DFFE + 1 3 1 1 min_003 (:44)
- 5 - C 21 DFFE + 1 3 1 3 min_002 (:45)
- 7 - C 22 DFFE + 1 3 1 2 min_001 (:46)
- 6 - C 22 DFFE + 1 1 1 4 min_000 (:47)
- 8 - C 24 DFFE + 1 3 1 1 min_113 (:48)
- 6 - C 24 DFFE + 1 3 1 3 min_112 (:49)
- 1 - C 22 DFFE + 1 4 1 3 min_111 (:50)
- 3 - C 22 DFFE + 1 1 1 3 min_110 (:51)
- 6 - C 15 AND2 0 4 0 11 :308
- 1 - C 07 AND2 0 4 0 6 :367
- 2 - C 13 AND2 0 4 0 6 :426
- 1 - C 19 AND2 0 4 0 3 :485
- 1 - C 21 AND2 0 4 0 3 :544
- 2 - C 22 OR2 s 0 2 0 2 ~603~1
- 1 - C 24 OR2 s 0 4 0 5 ~704~1
- 6 - C 21 AND2 s 0 2 0 5 ~770~1
- 3 - C 17 AND2 s 0 2 0 5 ~864~1
- 3 - C 13 OR2 0 4 0 1 :985
- 5 - C 07 AND2 s 0 2 0 3 ~1136~1
- 2 - C 07 OR2 0 4 0 1 :1136
- 3 - C 07 OR2 0 4 0 1 :1142
- 6 - C 07 OR2 0 3 0 1 :1148
- 1 - C 13 OR2 s 0 4 0 1 ~1345~1
- 8 - C 10 AND2 s ! 1 2 0 6 ~1351~1
- 6 - C 19 OR2 s 0 4 0 1 ~1357~1
- 5 - C 17 OR2 s 0 3 0 1 ~1369~1
- 8 - C 17 AND2 s ! 0 2 0 7 ~1375~1
- 8 - C 21 OR2 s 0 4 0 1 ~1381~1
- 8 - C 22 OR2 s 0 3 0 1 ~1393~1
- 2 - C 17 AND2 s ! 0 2 0 7 ~1399~1
- 7 - C 24 OR2 s 0 4 0 1 ~1405~1
- 4 - C 22 OR2 s 0 4 0 1 ~1417~1
- 5 - C 24 AND2 s ! 0 2 0 4 ~1423~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\yh1\watch.rpt
watch
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 12/ 96( 12%) 6/ 48( 12%) 22/ 48( 45%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\yh1\watch.rpt
watch
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 24 clk
Device-Specific Information: d:\yh1\watch.rpt
watch
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 24 reset
Device-Specific Information: d:\yh1\watch.rpt
watch
** EQUATIONS **
clk : INPUT;
reset : INPUT;
start : INPUT;
-- Node name is 'mic_00'
-- Equation name is 'mic_00', type is output
mic_00 = mic_000;
-- Node name is ':31' = 'mic_000'
-- Equation name is 'mic_000', location is LC1_C15, type is buried.
mic_000 = DFFE( _EQ001, GLOBAL( clk), !reset, VCC, VCC);
_EQ001 = mic_000 & !start
# !mic_000 & start;
-- Node name is ':30' = 'mic_001'
-- Equation name is 'mic_001', location is LC3_C15, type is buried.
mic_001 = DFFE( _EQ002, GLOBAL( clk), !reset, VCC, VCC);
_EQ002 = !_LC6_C15 & !mic_000 & mic_001
# !_LC6_C15 & mic_000 & !mic_001 & start
# mic_001 & !start;
-- Node name is 'mic_01'
-- Equation name is 'mic_01', type is output
mic_01 = mic_001;
-- Node name is ':29' = 'mic_002'
-- Equation name is 'mic_002', location is LC5_C15, type is buried.
mic_002 = DFFE( _EQ003, GLOBAL( clk), !reset, VCC, VCC);
_EQ003 = _LC2_C15 & !_LC6_C15 & start
# mic_002 & !start;
-- Node name is 'mic_02'
-- Equation name is 'mic_02', type is output
mic_02 = mic_002;
-- Node name is ':28' = 'mic_003'
-- Equation name is 'mic_003', location is LC7_C15, type is buried.
mic_003 = DFFE( _EQ004, GLOBAL( clk), !reset, VCC, VCC);
_EQ004 = !_LC6_C15 & !_LC8_C15 & mic_003
# !_LC6_C15 & _LC8_C15 & !mic_003 & start
# mic_003 & !start;
-- Node name is 'mic_03'
-- Equation name is 'mic_03', type is output
mic_03 = mic_003;
-- Node name is 'mic_10'
-- Equation name is 'mic_10', type is output
mic_10 = mic_110;
-- Node name is 'mic_11'
-- Equation name is 'mic_11', type is output
mic_11 = mic_111;
-- Node name is 'mic_12'
-- Equation name is 'mic_12', type is output
mic_12 = mic_112;
-- Node name is 'mic_13'
-- Equation name is 'mic_13', type is output
mic_13 = mic_113;
-- Node name is ':35' = 'mic_110'
-- Equation name is 'mic_110', location is LC5_C5, type is buried.
mic_110 = DFFE( _EQ005, GLOBAL( clk), !reset, VCC, VCC);
_EQ005 = !_LC6_C15 & mic_110
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