watch.vhd

2个按键的跑表

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity watch is
port(clk,reset,start: in std_logic;
     mic_0,mic_1,sec_0,sec_1,min_0,min_1: out std_logic_vector(3 downto 0));
end watch;
architecture behave of watch is
signal       mic_00:std_logic_vector(3 downto 0);
signal       mic_11:std_logic_vector(3 downto 0);
signal       sec_00:std_logic_vector(3 downto 0);
signal       sec_11:std_logic_vector(3 downto 0);
signal       min_00:std_logic_vector(3 downto 0);
signal       min_11:std_logic_vector(3 downto 0);
begin 
process(clk)
  begin
  if reset='1' then mic_00(3 downto 0)<="0000";
                    mic_11(3 downto 0)<="0000";
                    sec_00(3 downto 0)<="0000";
                    sec_11(3 downto 0)<="0000";
                    min_00(3 downto 0)<="0000";
                    min_11(3 downto 0)<="0000";
  else if clk'event and clk='1' then
          if start='1' then mic_00<=mic_00+1;
            if mic_00(3 downto 0)="1001" then
               mic_00(3 downto 0)<="0000";mic_11<=mic_11+1;
             if mic_11(3 downto 0)="1001" then
                mic_11(3 downto 0)<="0000";sec_00<=sec_00+1;
              if sec_00(3 downto 0)="1001" then
                 sec_00(3 downto 0)<="0000";sec_11<=sec_11+1;
                if sec_11(3 downto 0)="0101" then
                   sec_11(3 downto 0)<="0000";min_00<=min_00+1;
                 if min_00(3 downto 0)="1001" then
                    min_00(3 downto 0)<="0000";min_11<=min_11+1;
                  if min_11(3 downto 0)="0101" then
                     min_11(3 downto 0)<="0000";
                  end if; 
                 end if;
                end if;
               end if;
              end if;
             end if;
           end if;
         end if;
  end if;
end process;
mic_0<=mic_00;
mic_1<=mic_11;
sec_0<=sec_00;
sec_1<=sec_11;
min_0<=min_00;
min_1<=min_11;
end behave;