beep.fit.qmsg

一个verilog程序

{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 16 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  16 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 23 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  23 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 1 22 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  22 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 24 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.150 ns register register " "Info: Estimated most critical path is register to register delay of 5.150 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns buzzer:inst\|clk_div2\[3\] 1 REG LAB_X20_Y6 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X20_Y6; Fanout = 6; REG Node = 'buzzer:inst\|clk_div2\[3\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { buzzer:inst|clk_div2[3] } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/verilog/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.664 ns) + CELL(0.150 ns) 0.814 ns buzzer:inst\|Equal6~107 2 COMB LAB_X21_Y6 1 " "Info: 2: + IC(0.664 ns) + CELL(0.150 ns) = 0.814 ns; Loc. = LAB_X21_Y6; Fanout = 1; COMB Node = 'buzzer:inst\|Equal6~107'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.814 ns" { buzzer:inst|clk_div2[3] buzzer:inst|Equal6~107 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/verilog/beep/buzzer.v" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.290 ns) + CELL(0.275 ns) 1.379 ns buzzer:inst\|Equal6~108 3 COMB LAB_X21_Y6 3 " "Info: 3: + IC(0.290 ns) + CELL(0.275 ns) = 1.379 ns; Loc. = LAB_X21_Y6; Fanout = 3; COMB Node = 'buzzer:inst\|Equal6~108'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { buzzer:inst|Equal6~107 buzzer:inst|Equal6~108 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/verilog/beep/buzzer.v" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.290 ns) + CELL(0.275 ns) 1.944 ns buzzer:inst\|clk_div2\[6\]~2049 4 COMB LAB_X21_Y6 1 " "Info: 4: + IC(0.290 ns) + CELL(0.275 ns) = 1.944 ns; Loc. = LAB_X21_Y6; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2049'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { buzzer:inst|Equal6~108 buzzer:inst|clk_div2[6]~2049 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/verilog/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.150 ns) 2.509 ns buzzer:inst\|clk_div2\[6\]~2050 5 COMB LAB_X21_Y6 1 " "Info: 5: + IC(0.415 ns) + CELL(0.150 ns) = 2.509 ns; Loc. = LAB_X21_Y6; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2050'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { buzzer:inst|clk_div2[6]~2049 buzzer:inst|clk_div2[6]~2050 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/verilog/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.336 ns) + CELL(0.420 ns) 3.265 ns buzzer:inst\|clk_div2\[6\]~2052 6 COMB LAB_X20_Y6 1 " "Info: 6: + IC(0.336 ns) + CELL(0.420 ns) = 3.265 ns; Loc. = LAB_X20_Y6; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2052'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.756 ns" { buzzer:inst|clk_div2[6]~2050 buzzer:inst|clk_div2[6]~2052 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/verilog/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.436 ns) 3.828 ns buzzer:inst\|clk_div2\[6\]~2053 7 COMB LAB_X20_Y6 1 " "Info: 7: + IC(0.127 ns) + CELL(0.436 ns) = 3.828 ns; Loc. = LAB_X20_Y6; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2053'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.563 ns" { buzzer:inst|clk_div2[6]~2052 buzzer:inst|clk_div2[6]~2053 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/verilog/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.150 ns) 4.393 ns buzzer:inst\|clk_div2\[6\]~2054 8 COMB LAB_X20_Y6 13 " "Info: 8: + IC(0.415 ns) + CELL(0.150 ns) = 4.393 ns; Loc. = LAB_X20_Y6; Fanout = 13; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2054'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { buzzer:inst|clk_div2[6]~2053 buzzer:inst|clk_div2[6]~2054 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/verilog/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.247 ns) + CELL(0.510 ns) 5.150 ns buzzer:inst\|clk_div2\[10\] 9 REG LAB_X20_Y6 8 " "Info: 9: + IC(0.247 ns) + CELL(0.510 ns) = 5.150 ns; Loc. = LAB_X20_Y6; Fanout = 8; REG Node = 'buzzer:inst\|clk_div2\[10\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.757 ns" { buzzer:inst|clk_div2[6]~2054 buzzer:inst|clk_div2[10] } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/verilog/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.366 ns ( 45.94 % ) " "Info: Total cell delay = 2.366 ns ( 45.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.784 ns ( 54.06 % ) " "Info: Total interconnect delay = 2.784 ns ( 54.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.150 ns" { buzzer:inst|clk_div2[3] buzzer:inst|Equal6~107 buzzer:inst|Equal6~108 buzzer:inst|clk_div2[6]~2049 buzzer:inst|clk_div2[6]~2050 buzzer:inst|clk_div2[6]~2052 buzzer:inst|clk_div2[6]~2053 buzzer:inst|clk_div2[6]~2054 buzzer:inst|clk_div2[10] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x14_y0 x28_y14 " "Info: The peak interconnect region extends from location x14_y0 to location x28_y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "1 " "Warning: Found 1 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "beep 0 " "Info: Pin \"beep\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 20 12:55:58 2008 " "Info: Processing ended: Sat Dec 20 12:55:58 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/verilog/beep/beep.fit.smsg " "Info: Generated suppressed messages file D:/verilog/beep/beep.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}