div_2n.vhd

来自「此程序实现的是任意进制的分频 进制的输入是任意选择的」· VHDL 代码 · 共 38 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div_2n is 
port(clk:in std_logic;---shizhongxinhao
     p:in std_logic_vector(7 downto 0);
     div2n:out std_logic);
end;
architecture one of div_2n is 
    signal cnt: std_logic_vector(7 downto 0);---n bu da yu 2 de m ci fang ;
    signal clk_temp: std_logic;
    signal m: std_logic_vector(7 downto 0);---kong zhi ji shu qi de chang liang;
begin
process(p)
begin 
  m<=p-1;
end process;
     
    

     
  
process(clk)

begin
     if clk'event and clk='1'  then 
        if cnt=m then 
               clk_temp<='1';---fanzhuan
               cnt<="00000000";
        else 
           cnt<=cnt+1;
           clk_temp<='0';
        end if;
    end if;
end process;
div2n<=clk_temp;
end;