div_2n.vhd.bak

此程序实现的是任意进制的分频 进制的输入是任意选择的

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div_2n is 
port(clk,set:in std_logic;---shizhongxinhao
     p:in std_logic_vector(7 downto 0);
     div2n:out std_logic);
end;
architecture one of div_2n is 
    signal cnt: std_logic_vector(7 downto 0);---n bu da yu 2 de m ci fang ;
    signal clk_temp: std_logic;
    signal m: std_logic_vector(7 downto 0);---kong zhi ji shu qi de chang liang;
begin
process(p)
begin 
  case p is
     when "00000010"=> m<="00000001";
     when "00000011"=> m<="00000010";
     when "00000100"=> m<="00000011";
     when "00000101"=> m<="00000100";
     when "00000110"=> m<="00000101";
     when "00000111"=> m<="00000110";
     when "00001000"=> m<="00000111";
     when "00001001"=> m<="00001000";
     when "00001010"=> m<="00001001";
     when "00001011"=> m<="00001010";
     when "00001100"=> m<="00001011";
     when "00001101"=> m<="00001100";
     when "00001110"=> m<="00001101";
     when "00001111"=> m<="00001110";
     when others=>null;
end case;
end process;
     
    

     
  
process(clk)

begin
     if clk'event and clk='1'  then 
        if cnt=m then 
               clk_temp<= not clk_temp;---fanzhuan
               cnt<="00000000";
        else 
           cnt<=cnt+1;
        end if;
    end if;
end process;
div2n<=clk_temp;
end;