keylock.tan.rpt

时间以60分种为一个周期 电子钟的格式为：XX XX XX

+------------------------------+------------------------------------------+---------------+----------------------------------+---------------------------------------------------------------------+-----------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1K30TC144-3      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK_40M         ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK_40M'                                                                                                                                                                                                                                                                                                                               ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------+---------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                               ; To                                                                  ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------+---------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; CONTROLER:U3|ACC[6]                                                ; CONTROLER:U3|QA                                                     ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 9.600 ns                ;
; N/A                                     ; 64.94 MHz ( period = 15.400 ns )                    ; CONTROLER:U3|ACC[6]                                                ; CONTROLER:U3|QB                                                     ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 9.400 ns                ;
; N/A                                     ; 64.94 MHz ( period = 15.400 ns )                    ; CONTROLER:U3|ACC[15]                                               ; CONTROLER:U3|QA                                                     ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 9.400 ns                ;
; N/A                                     ; 64.94 MHz ( period = 15.400 ns )                    ; CONTROLER:U3|ACC[10]                                               ; CONTROLER:U3|QA                                                     ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 9.400 ns                ;
; N/A                                     ; 65.79 MHz ( period = 15.200 ns )                    ; CONTROLER:U3|ACC[15]                                               ; CONTROLER:U3|QB                                                     ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 9.200 ns                ;
; N/A                                     ; 65.79 MHz ( period = 15.200 ns )                    ; CONTROLER:U3|ACC[10]                                               ; CONTROLER:U3|QB                                                     ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 9.200 ns                ;
; N/A                                     ; 65.79 MHz ( period = 15.200 ns )                    ; CONTROLER:U3|ACC[11]                                               ; CONTROLER:U3|QA                                                     ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 9.200 ns                ;
; N/A                                     ; 66.67 MHz ( period = 15.000 ns )                    ; CONTROLER:U3|ACC[11]                                               ; CONTROLER:U3|QB                                                     ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 9.000 ns                ;
; N/A                                     ; 66.67 MHz ( period = 15.000 ns )                    ; CONTROLER:U3|ACC[8]                                                ; CONTROLER:U3|QA                                                     ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 9.000 ns                ;