debouncing.vhd

来自「时间以60分种为一个周期 电子钟的格式为：XX XX XX」· VHDL 代码 · 共 30 行

LIBRARY ieee; 
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY altera;     --打开altera专用库
USE altera.maxplus2.ALL; 

ENTITY debouncing IS 
PORT 
(d_in, clk : IN STD_LOGIC; 
 d_out: OUT STD_LOGIC 
); 
END debouncing ; 
ARCHITECTURE art OF debouncing IS 
signal vcc, inv_d : std_logic ; 
signal q0, q1 : std_logic ; --状态信号
signal d1, d0 : std_logic ; 输出信号
BEGIN 
vcc <='1' ; 
inv_d <= not d_in ; 
--接入双D触发器，对输入信号进行处理
dff1 : dff PORT MAP (d =>vcc , q => q0 , clk => clk, clrn => inv_d , prn => vcc); 
dff2 : dff PORT MAP (d =>vcc , q => q1, clk => clk, clrn => q0 , prn => vcc); 
process (clk) 
begin 
if clk'event and clk='1' then 
d0 <= not q1; 
d1 <= d0; 
end if ;