signal

本程序包含：EEPROM的功能模型(eeprom.v)、读/写EEPROM的verilog HDL 行为模块（eeprom_wr.v）、信号产生模块（signal.v）和顶层模块(top.v)

`timescale 1ns/1ns
`difine timeslice 200
module Signal(RESET,CLK,RD,WR,ADDR,ACK,DATA);
output RESET;
output CLK;
output RD,WR;
output[10:0]ADDR;
input ACK;
inout[7:0] DATA;
reg RESET;
reg CLK;`timescale 1ns/1ns
        `difine timeslice 200
        module Signal(RESET,CLK,RD,WR,ADDR,ACK,DATA);
        output RESET;
        output CLK;
        output RD,WR;
        output[10:0]ADDR;
        input ACK;
        inout[7:0] DATA;
        reg RESET;
        reg CLK;
        reg RD,WR;
        reg W_R;
        reg[10:0]ADDR;
        reg[7:0]data_to_eeprom;
        reg[10:0]addr_mem[0:255];
        reg[7:0] data_mem[0:255];
        reg[7:0] ROM[0:2047];
        integer i,j;
        integer OUTFILE;
        assign DATA=(W_R)?8'bz:data_to_eeprom;
        
        //-----??????-----
        always@(`timeslice/2)
        CLK=~CLK;
        //-----??????----
        initial
            begin
                RESET=1;
                i=0;
                j=0;
                W_R=0;
                CLK=0;
                RD=0;
                WR=0;
                #1000;
                RESET=0;
                repeat(15)
                     begin
                         #(5*`timeslice);
                         WR=1;
                         #(`timeslice);
                         WR=0;
                         @(posedge ACK)
                     end
                     #(10*`timeslice);
                     W_R=1;
                     repeat(15)
                     begin
                         #(5*`timeslice)
                         RD=1;
                         #(`timeslice);
                         RD=0;
                         @(posedge ACK);
                     end
                 end
          //-------???---
          initial
          begin
             $display("writing---writing---writing---writing");
             #(2*`timeslice);
             for(i=0;i<=15;i=i+1)
               begin
                   ADDR=addr_mem[i];
                   data_to_eeprom=data_mem[i];
                   $fdisplay(OUTFILE,"@%0h  %0h",ADDR,data_to_eeprom);
                   @(posedge ACK);
               end
           end        
        
        //------???----
        initial
          @(posedge W_R)
            begin
                ADDR=addr_men[0];
                $fclose(OUTFILE);
                $readmenh("./eeprom.dat",ROM);
                $display("Begin READING---READING---READING---READING");
                 for(j=0;j<=15;j=j+1)
                   begin
                       ADDR=addr_mem[j];
                       @(posedge ACK);
                       if(DATA==ROM[ADDR])
                          $display("DATA %0h==ROM[%0h]---READ RIGHT",DATA,ADDR);
                        else
                          $display("DATA %0h!=ROM[%0h]---READ WRONG",DATA,ADDR);
                    end
                end
        
reg RD,WR;
reg W_R;
reg[10:0]ADDR;
reg[7:0]data_to_eeprom;
reg[10:0]addr_mem[0:255];
reg[7:0] data_mem[0:255];
reg[7:0] ROM[0:2047];
integer i,j;
integer OUTFILE;
assign DATA=(W_R)?8'bz:data_to_eeprom;

//-----??????-----
always@(`timeslice/2)
CLK=~CLK;
//-----??????----
initial
    begin
        RESET=1;
        i=0;
        j=0;
        W_R=0;
        CLK=0;
        RD=0;
        WR=0;
        #1000;
        RESET=0;
        repeat(15)
             begin
                 #(5*`timeslice);
                 WR=1;
                 #(`timeslice);
                 WR=0;
                 @(posedge ACK)
             end
             #(10*`timeslice);
             W_R=1;
             repeat(15)
             begin
                 #(5*`timeslice)
                 RD=1;
                 #(`timeslice);
                 RD=0;
                 @(posedge ACK);
             end
         end
  //-------???---
  initial
  begin
     $display("writing---writing---writing---writing");
     #(2*`timeslice);
     for(i=0;i<=15;i=i+1)
       begin
           ADDR=addr_mem[i];
           data_to_eeprom=data_mem[i];
           $fdisplay(OUTFILE,"@%0h  %0h",ADDR,data_to_eeprom);
           @(posedge ACK);
       end
   end        

//------???----
initial
  @(posedge W_R)
    begin
        ADDR=addr_men[0];
        $fclose(OUTFILE);
        $readmenh("./eeprom.dat",ROM);
        $display("Begin READING---READING---READING---READING");
         for(j=0;j<=15;j=j+1)
           begin
               ADDR=addr_mem[j];
               @(posedge ACK);
               if(DATA==ROM[ADDR])
                  $display("DATA %0h==ROM[%0h]---READ RIGHT",DATA,ADDR);
                else
                  $display("DATA %0h!=ROM[%0h]---READ WRONG",DATA,ADDR);
            end
        end


 initial
 begin
     OUTFILE=$fopen("./eeprom.dat");
     $readmemh("./addr.dat",addr_menm);
     $readmemh("./data.dat",data_mem);
 end
 endmodule