📄 cnt10.rpt
字号:
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\vhdl编程\cnt10_t\cnt10.rpt
cnt10
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - C 05 AND2 0 2 0 1 |LPM_ADD_SUB:69|addcore:adder|:55
- 1 - C 05 DFFE + 0 3 1 1 Q3 (:8)
- 3 - C 05 DFFE + 0 3 1 2 Q2 (:9)
- 5 - C 05 DFFE + 0 2 1 3 Q1 (:10)
- 7 - C 05 DFFE + 1 0 1 4 Q0 (:11)
- 2 - C 05 OR2 s 0 3 0 1 ~44~1
- 4 - C 05 OR2 s 1 2 0 3 ~123~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\vhdl编程\cnt10_t\cnt10.rpt
cnt10
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 1/ 96( 1%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\vhdl编程\cnt10_t\cnt10.rpt
cnt10
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 CLK
Device-Specific Information: d:\vhdl编程\cnt10_t\cnt10.rpt
cnt10
** EQUATIONS **
CLK : INPUT;
CLR : INPUT;
-- Node name is 'QOUT0'
-- Equation name is 'QOUT0', type is output
QOUT0 = Q0;
-- Node name is 'QOUT1'
-- Equation name is 'QOUT1', type is output
QOUT1 = Q1;
-- Node name is 'QOUT2'
-- Equation name is 'QOUT2', type is output
QOUT2 = Q2;
-- Node name is 'QOUT3'
-- Equation name is 'QOUT3', type is output
QOUT3 = Q3;
-- Node name is ':11' = 'Q0'
-- Equation name is 'Q0', location is LC7_C5, type is buried.
Q0 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = !CLR & !Q0;
-- Node name is ':10' = 'Q1'
-- Equation name is 'Q1', location is LC5_C5, type is buried.
Q1 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = _LC4_C5 & !Q0 & Q1
# _LC4_C5 & Q0 & !Q1;
-- Node name is ':9' = 'Q2'
-- Equation name is 'Q2', location is LC3_C5, type is buried.
Q2 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = _LC4_C5 & !Q1 & Q2
# _LC4_C5 & !Q0 & Q2
# _LC4_C5 & Q0 & Q1 & !Q2;
-- Node name is ':8' = 'Q3'
-- Equation name is 'Q3', location is LC1_C5, type is buried.
Q3 = DFFE( _EQ004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = _LC4_C5 & !_LC6_C5 & Q3
# _LC4_C5 & !Q2 & Q3
# _LC4_C5 & _LC6_C5 & Q2 & !Q3;
-- Node name is '|LPM_ADD_SUB:69|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C5', type is buried
_LC6_C5 = LCELL( _EQ005);
_EQ005 = Q0 & Q1;
-- Node name is '~44~1'
-- Equation name is '~44~1', location is LC2_C5, type is buried.
-- synthesized logic cell
_LC2_C5 = LCELL( _EQ006);
_EQ006 = Q1
# !Q3
# !Q0;
-- Node name is '~123~1'
-- Equation name is '~123~1', location is LC4_C5, type is buried.
-- synthesized logic cell
_LC4_C5 = LCELL( _EQ007);
_EQ007 = !CLR & Q2
# !CLR & _LC2_C5;
Project Information d:\vhdl编程\cnt10_t\cnt10.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,280K
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