clk_div.vhd

来自「这是我在ISP编程实验中独立编写的一个采用行为描述方式实现的分频器」· VHDL 代码 · 共 36 行

LIBRARY ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

ENTITY clk_div IS
  PORT (clk:IN std_logic;
        clk_div16:OUT std_logic );
END clk_div;
ARCHITECTURE rtl OF clk_div IS
SIGNAL count: std_logic_vector(3 DOWNTO 0);
BEGIN
 PROCESS(clk)
  BEGIN
   IF (clk'EVENT AND clk = '1' ) THEN
    IF (count = "0011") THEN
count <="0000";

--        count <=(others => '0' );
    ELSE
        count <= count + 1;
    END IF;
   END IF;
  END PROCESS;
 PROCESS (clk)
 BEGIN
  IF (clk'EVENT AND clk = '1' ) THEN
    IF (count = "0011") THEN
      clk_div16 <= '1';
    ELSE
      clk_div16 <= '0';
    END IF;
   END IF;
  END PROCESS;
END rtl;