📄 seven.rpt
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* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\isp\seven\seven.rpt
seven
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
A4 : INPUT;
A5 : INPUT;
A6 : INPUT;
-- Node name is 'G'
-- Equation name is 'G', location is LC023, type is output.
G = LCELL( _EQ001 $ GND);
_EQ001 = _LC004 & !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 &
!_LC025 & !_LC029 & !_LC030 & !_LC031 & !_LC032
# !_LC004 & _LC028;
-- Node name is 'R'
-- Equation name is 'R', location is LC027, type is output.
R = LCELL( _EQ002 $ VCC);
_EQ002 = _LC004 & !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 &
!_LC025 & !_LC029 & !_LC030 & !_LC031 & !_LC032
# !_LC004 & _LC028;
-- Node name is '|LPM_ADD_SUB:159|addcore:adder|addcore:adder0|gs1' from file "addcore.tdf" line 148, column 7
-- Equation name is '_LC016', type is buried
_LC016 = LCELL( _EQ003 $ A0);
_EQ003 = !A0 & A1 & A2
# A0 & !A1 & !A2;
-- Node name is '|LPM_ADD_SUB:159|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC001', type is buried
_LC001 = LCELL( _EQ004 $ GND);
_EQ004 = A0 & A2
# A1 & A2
# A0 & A1;
-- Node name is '|LPM_ADD_SUB:194|addcore:adder|addcore:adder0|ps2' from file "addcore.tdf" line 150, column 7
-- Equation name is '_LC024', type is buried
_LC024 = LCELL( _EQ005 $ !_LC001);
_EQ005 = !A3 & !A4 & _LC001
# !A3 & !A5 & _LC001
# !A4 & !A5 & _LC001;
-- Node name is '|LPM_ADD_SUB:194|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC002', type is buried
_LC002 = LCELL( _LC024 $ _EQ006);
_EQ006 = !_LC003 & !_LC026 & _X001 & _X002;
_X001 = EXP( A3 & !A4 & A5 & !_LC016);
_X002 = EXP( A3 & A4 & !_LC016);
-- Node name is '|LPM_ADD_SUB:194|addcore:adder|addcore:adder0|~245~1~2' from file "addcore.tdf" line 392, column 42
-- Equation name is '_LC026', type is buried
-- synthesized logic cell
_LC026 = LCELL( _EQ007 $ GND);
_EQ007 = !A0 & A1 & A2 & !A3 & !A4
# A0 & !A1 & A2 & !A3 & !A4
# !A0 & A1 & A2 & !A3 & !A5
# A0 & !A1 & A2 & !A3 & !A5
# !A0 & A1 & A2 & !A4 & !A5;
-- Node name is '|LPM_ADD_SUB:194|addcore:adder|addcore:adder0|~245~1~3' from file "addcore.tdf" line 392, column 42
-- Equation name is '_LC003', type is buried
-- synthesized logic cell
_LC003 = LCELL( _EQ008 $ GND);
_EQ008 = A0 & !A1 & A2 & !A4 & !A5
# A0 & A1 & !A3 & !A4
# A0 & A1 & !A3 & !A5
# A0 & A1 & !A4 & !A5
# !A3 & A4 & A5 & !_LC016;
-- Node name is '~233~1'
-- Equation name is '~233~1', location is LC028, type is buried.
-- synthesized logic cell
_LC028 = LCELL( _EQ009 $ _EQ010);
_EQ009 = A0 & A1 & A2 & A3 & A4 & A5 & !_LC002 & !_LC017 & !_LC018 &
!_LC019 & !_LC020 & !_LC021 & !_LC025 & !_LC029 & !_LC030 &
!_LC031
# A0 & !A1 & A2 & !A3 & A4 & A5 & !_LC001 & !_LC017 & !_LC018 &
!_LC019 & !_LC020 & !_LC021 & !_LC025 & !_LC029 & !_LC030 &
!_LC031
# A0 & A1 & !A2 & !A3 & A4 & A5 & !_LC001 & !_LC017 & !_LC018 &
!_LC019 & !_LC020 & !_LC021 & !_LC025 & !_LC029 & !_LC030 &
!_LC031
# !A0 & A1 & A2 & !A3 & A4 & A5 & !_LC001 & !_LC017 & !_LC018 &
!_LC019 & !_LC020 & !_LC021 & !_LC025 & !_LC029 & !_LC030 &
!_LC031;
_EQ010 = !_LC017 & !_LC018 & !_LC019 & !_LC020 & !_LC021 & !_LC025 &
!_LC029 & !_LC030 & !_LC031;
-- Node name is '~233~2'
-- Equation name is '~233~2', location is LC030, type is buried.
-- synthesized logic cell
_LC030 = LCELL( _EQ011 $ GND);
_EQ011 = A0 & A1 & !A2 & A3 & !A4 & A5 & !_LC001
# A0 & A1 & !A2 & A3 & A4 & !A5 & !_LC001
# A0 & !A1 & A2 & A3 & !A4 & A5 & !_LC001
# A0 & !A1 & A2 & A3 & A4 & !A5 & !_LC001
# !A0 & A1 & A2 & A3 & !A4 & A5 & !_LC001;
-- Node name is '~233~3'
-- Equation name is '~233~3', location is LC031, type is buried.
-- synthesized logic cell
_LC031 = LCELL( _EQ012 $ GND);
_EQ012 = !A0 & A1 & A2 & A3 & A4 & !A5 & !_LC001
# !A0 & !A1 & A2 & A3 & A4 & A5 & !_LC002
# A0 & !A1 & !A2 & A3 & A4 & A5 & !_LC002
# !A0 & A1 & !A2 & A3 & A4 & A5 & !_LC002
# !A0 & !A1 & !A2 & A3 & A4 & !A5 & !_LC001;
-- Node name is '~233~4'
-- Equation name is '~233~4', location is LC029, type is buried.
-- synthesized logic cell
_LC029 = LCELL( _EQ013 $ GND);
_EQ013 = !A0 & !A1 & !A2 & A3 & !A4 & A5 & !_LC001
# !A0 & !A1 & !A2 & !A3 & A4 & A5 & !_LC001
# A0 & A1 & !A2 & !A3 & !A4 & !A5
# A0 & !A1 & A2 & !A3 & !A4 & !A5
# !A0 & A1 & A2 & !A3 & !A4 & !A5;
-- Node name is '~233~5'
-- Equation name is '~233~5', location is LC025, type is buried.
-- synthesized logic cell
_LC025 = LCELL( _EQ014 $ GND);
_EQ014 = A0 & A1 & !A2 & !A3 & !A4 & !A6
# A0 & A1 & !A2 & !A3 & !A5 & !A6
# A0 & A1 & !A2 & !A4 & !A5 & !A6
# A0 & !A1 & A2 & !A3 & !A4 & !A6
# A0 & !A1 & A2 & !A3 & !A5 & !A6;
-- Node name is '~233~6'
-- Equation name is '~233~6', location is LC017, type is buried.
-- synthesized logic cell
_LC017 = LCELL( _EQ015 $ GND);
_EQ015 = A0 & !A1 & A2 & !A4 & !A5 & !A6
# !A0 & A1 & A2 & !A3 & !A4 & !A6
# !A0 & A1 & A2 & !A3 & !A5 & !A6
# !A0 & A1 & A2 & !A4 & !A5 & !A6
# !A0 & !A1 & !A2 & !A3 & !A4 & !A5;
-- Node name is '~233~7'
-- Equation name is '~233~7', location is LC018, type is buried.
-- synthesized logic cell
_LC018 = LCELL( _EQ016 $ GND);
_EQ016 = !A0 & !A1 & !A2 & !A3 & !A4 & !A6
# !A0 & !A1 & !A2 & !A3 & !A5 & !A6
# !A0 & !A1 & !A2 & !A4 & !A5 & !A6
# A3 & A4 & A5 & A6 & !_LC002
# A0 & A1 & A2 & A6 & !_LC002;
-- Node name is '~233~8'
-- Equation name is '~233~8', location is LC019, type is buried.
-- synthesized logic cell
_LC019 = LCELL( _EQ017 $ GND);
_EQ017 = !A0 & A1 & !A2 & A6 & !_LC002
# A0 & !A1 & !A2 & A6 & !_LC002
# !A0 & !A1 & A2 & A6 & !_LC002
# A0 & A1 & !A2 & !A6 & !_LC001
# A0 & !A1 & A2 & !A6 & !_LC001;
-- Node name is '~233~9'
-- Equation name is '~233~9', location is LC020, type is buried.
-- synthesized logic cell
_LC020 = LCELL( _EQ018 $ GND);
_EQ018 = !A0 & A1 & A2 & !A6 & !_LC001
# A3 & A4 & !A5 & !A6 & !_LC001
# A3 & !A4 & A5 & !A6 & !_LC001
# !A3 & A4 & A5 & !A6 & !_LC001
# !A0 & !A1 & !A2 & !A6 & !_LC001;
-- Node name is '~233~10'
-- Equation name is '~233~10', location is LC021, type is buried.
-- synthesized logic cell
_LC021 = LCELL( _EQ019 $ GND);
_EQ019 = !A3 & !A4 & !A5 & !A6
# !A3 & !A4 & !_LC002
# !A3 & !A5 & !_LC002
# !A4 & !A5 & !_LC002
# !_LC001 & !_LC002;
-- Node name is '~236~1'
-- Equation name is '~236~1', location is LC004, type is buried.
-- synthesized logic cell
_LC004 = LCELL( _EQ020 $ !A0);
_EQ020 = !_LC005 & !_LC006 & !_LC007 & !_LC008 & !_LC012 & !_LC022 & _X003 &
_X004;
_X003 = EXP(!A1 & !A2 & !A3 & A4 & !A5 & !A6);
_X004 = EXP(!A1 & !A2 & !A3 & !A4 & A5 & !A6);
-- Node name is '~236~2'
-- Equation name is '~236~2', location is LC022, type is buried.
-- synthesized logic cell
_LC022 = LCELL( _EQ021 $ GND);
_EQ021 = A1 & !A2 & A3 & A4 & A5 & A6
# A1 & A2 & A3 & !A4 & A5 & A6
# A1 & A2 & A3 & A4 & !A5 & A6
# A1 & A2 & A3 & A4 & A5 & !A6
# A1 & A2 & !A3 & A4 & A5 & A6;
-- Node name is '~236~3'
-- Equation name is '~236~3', location is LC005, type is buried.
-- synthesized logic cell
_LC005 = LCELL( _EQ022 $ GND);
_EQ022 = !A1 & A2 & A3 & A4 & A5 & A6
# A1 & !A2 & A3 & !A4 & !A5 & A6
# A1 & !A2 & !A3 & A4 & !A5 & A6
# A1 & !A2 & !A3 & !A4 & A5 & A6
# A1 & A2 & !A3 & !A4 & !A5 & A6;
-- Node name is '~236~4'
-- Equation name is '~236~4', location is LC006, type is buried.
-- synthesized logic cell
_LC006 = LCELL( _EQ023 $ GND);
_EQ023 = A1 & !A2 & A3 & A4 & !A5 & !A6
# A1 & !A2 & A3 & !A4 & A5 & !A6
# A1 & !A2 & !A3 & A4 & A5 & !A6
# A1 & A2 & A3 & !A4 & !A5 & !A6
# A1 & A2 & !A3 & A4 & !A5 & !A6;
-- Node name is '~236~5'
-- Equation name is '~236~5', location is LC007, type is buried.
-- synthesized logic cell
_LC007 = LCELL( _EQ024 $ GND);
_EQ024 = A1 & A2 & !A3 & !A4 & A5 & !A6
# !A1 & A2 & A3 & !A4 & !A5 & A6
# !A1 & A2 & !A3 & A4 & !A5 & A6
# !A1 & A2 & !A3 & !A4 & A5 & A6
# !A1 & A2 & A3 & A4 & !A5 & !A6;
-- Node name is '~236~6'
-- Equation name is '~236~6', location is LC008, type is buried.
-- synthesized logic cell
_LC008 = LCELL( _EQ025 $ GND);
_EQ025 = !A1 & A2 & A3 & !A4 & A5 & !A6
# !A1 & A2 & !A3 & A4 & A5 & !A6
# !A1 & !A2 & A3 & A4 & !A5 & A6
# !A1 & !A2 & A3 & !A4 & A5 & A6
# !A1 & !A2 & A3 & A4 & A5 & !A6;
-- Node name is '~236~7'
-- Equation name is '~236~7', location is LC012, type is buried.
-- synthesized logic cell
_LC012 = LCELL( _EQ026 $ GND);
_EQ026 = !A1 & !A2 & !A3 & A4 & A5 & A6
# !A1 & !A2 & !A3 & !A4 & !A5 & A6
# A1 & !A2 & !A3 & !A4 & !A5 & !A6
# !A1 & A2 & !A3 & !A4 & !A5 & !A6
# !A1 & !A2 & A3 & !A4 & !A5 & !A6;
-- Node name is '~257~1'
-- Equation name is '~257~1', location is LC032, type is buried.
-- synthesized logic cell
_LC032 = LCELL( _EQ027 $ GND);
_EQ027 = A0 & A1 & A2 & A3 & A4 & A5 & !_LC002
# A0 & A1 & !A2 & !A3 & A4 & A5 & !_LC001
# A0 & !A1 & A2 & !A3 & A4 & A5 & !_LC001
# !A0 & A1 & A2 & !A3 & A4 & A5 & !_LC001;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\isp\seven\seven.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = on
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,861K
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