seven.rpt

这是我在ISP编程实验中独立编写的采用结构化描述的一个七人表决器

Project Information                                     d:\isp\seven\seven.rpt

MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 12/14/2008 22:17:56

Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful


SEVEN


** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

seven     EPM7032LC44-6    7        2        0      26      4           81 %

User Pins:                 7        2        0  



Project Information                                     d:\isp\seven\seven.rpt

** FILE HIERARCHY **



|lpm_add_sub:124|
|lpm_add_sub:124|addcore:adder|
|lpm_add_sub:124|addcore:adder|addcore:adder0|
|lpm_add_sub:124|altshift:result_ext_latency_ffs|
|lpm_add_sub:124|altshift:carry_ext_latency_ffs|
|lpm_add_sub:124|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:159|
|lpm_add_sub:159|addcore:adder|
|lpm_add_sub:159|addcore:adder|addcore:adder0|
|lpm_add_sub:159|altshift:result_ext_latency_ffs|
|lpm_add_sub:159|altshift:carry_ext_latency_ffs|
|lpm_add_sub:159|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:194|
|lpm_add_sub:194|addcore:adder|
|lpm_add_sub:194|addcore:adder|addcore:adder0|
|lpm_add_sub:194|altshift:result_ext_latency_ffs|
|lpm_add_sub:194|altshift:carry_ext_latency_ffs|
|lpm_add_sub:194|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:229|
|lpm_add_sub:229|addcore:adder|
|lpm_add_sub:229|addcore:adder|addcore:adder0|
|lpm_add_sub:229|altshift:result_ext_latency_ffs|
|lpm_add_sub:229|altshift:carry_ext_latency_ffs|
|lpm_add_sub:229|altshift:oflow_ext_latency_ffs|
|f_adder:u1|
|f_adder:u1|adder:u1|
|f_adder:u1|adder:u2|
|f_adder:u1|or2a:u3|
|f_adder:u2|
|f_adder:u2|adder:u1|
|f_adder:u2|adder:u2|
|f_adder:u2|or2a:u3|
|f_adder:u3|
|f_adder:u3|adder:u1|
|f_adder:u3|adder:u2|
|f_adder:u3|or2a:u3|


Device-Specific Information:                            d:\isp\seven\seven.rpt
seven

***** Logic for device 'seven' compiled without errors.




Device: EPM7032LC44-6

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF

                                         R  R  
                                         E  E  
                                         S  S  
                                         E  E  
                                         R  R  
                       V  G  G  G  G  G  V  V  
              A  A  A  C  N  N  N  N  N  E  E  
              5  6  0  C  D  D  D  D  D  D  D  
            -----------------------------------_ 
          /   6  5  4  3  2  1 44 43 42 41 40   | 
      A4 |  7                                39 | RESERVED 
      A3 |  8                                38 | RESERVED 
      A2 |  9                                37 | RESERVED 
     GND | 10                                36 | RESERVED 
      A1 | 11                                35 | VCC 
RESERVED | 12         EPM7032LC44-6          34 | G 
RESERVED | 13                                33 | RESERVED 
RESERVED | 14                                32 | RESERVED 
     VCC | 15                                31 | RESERVED 
RESERVED | 16                                30 | GND 
RESERVED | 17                                29 | R 
         |_  18 19 20 21 22 23 24 25 26 27 28  _| 
           ------------------------------------ 
              R  R  R  R  G  V  R  R  R  R  R  
              E  E  E  E  N  C  E  E  E  E  E  
              S  S  S  S  D  C  S  S  S  S  S  
              E  E  E  E        E  E  E  E  E  
              R  R  R  R        R  R  R  R  R  
              V  V  V  V        V  V  V  V  V  
              E  E  E  E        E  E  E  E  E  
              D  D  D  D        D  D  D  D  D  


N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.



Device-Specific Information:                            d:\isp\seven\seven.rpt
seven

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16    10/16( 62%)   7/16( 43%)  10/16( 62%)  17/36( 47%) 
B:    LC17 - LC32    16/16(100%)   2/16( 12%)  12/16( 75%)  21/36( 58%) 


Total dedicated input pins used:                 0/4      (  0%)
Total I/O pins used:                             9/32     ( 28%)
Total logic cells used:                         26/32     ( 81%)
Total shareable expanders used:                  4/32     ( 12%)
Total Turbo logic cells used:                   26/32     ( 81%)
Total shareable expanders not available (n/a):  18/32     ( 56%)
Average fan-in:                                  7.38
Total fan-in:                                   192

Total input pins required:                       7
Total output pins required:                      2
Total bidirectional pins required:               0
Total logic cells required:                     26
Total flipflops required:                        0
Total product terms required:                  116
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:           4

Synthesized logic cells:                        20/  32   ( 62%)



Device-Specific Information:                            d:\isp\seven\seven.rpt
seven

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   4    (1)  (A)      INPUT               0      0   0    0    0    0   15  A0
  11    (7)  (A)      INPUT               0      0   0    0    0    0   21  A1
   9    (6)  (A)      INPUT               0      0   0    0    0    0   21  A2
   8    (5)  (A)      INPUT               0      0   0    0    0    0   21  A3
   7    (4)  (A)      INPUT               0      0   0    0    0    0   21  A4
   6    (3)  (A)      INPUT               0      0   0    0    0    0   21  A5
   5    (2)  (A)      INPUT               0      0   0    0    0    0   13  A6


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                            d:\isp\seven\seven.rpt
seven

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  34     23    B     OUTPUT      t        0      0   0    0   12    0    0  G
  29     27    B     OUTPUT      t        0      0   0    0   12    0    0  R


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                            d:\isp\seven\seven.rpt
seven

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (21)    16    A       SOFT      t        0      0   0    3    0    0    2  |LPM_ADD_SUB:159|addcore:adder|addcore:adder0|gs1
  (4)     1    A       SOFT      t        0      0   0    3    0    0    9  |LPM_ADD_SUB:159|addcore:adder|addcore:adder0|result_node2
 (33)    24    B       SOFT      t        0      0   0    3    1    0    1  |LPM_ADD_SUB:194|addcore:adder|addcore:adder0|ps2
  (5)     2    A       SOFT      t        2      0   0    3    4    0    6  |LPM_ADD_SUB:194|addcore:adder|addcore:adder0|result_node2
 (31)    26    B       SOFT    s t        1      0   1    6    0    0    1  |LPM_ADD_SUB:194|addcore:adder|addcore:adder0|~245~1~2
  (6)     3    A       SOFT    s t        1      0   1    6    1    0    1  |LPM_ADD_SUB:194|addcore:adder|addcore:adder0|~245~1~3
 (28)    28    B       SOFT    s t        1      0   1    6   11    2    0  ~233~1
 (26)    30    B       SOFT    s t        1      0   1    6    1    2    1  ~233~2
 (25)    31    B       SOFT    s t        1      0   1    6    2    2    1  ~233~3
 (27)    29    B       SOFT    s t        1      0   1    6    1    2    1  ~233~4
 (32)    25    B       SOFT    s t        1      0   1    7    0    2    1  ~233~5
 (41)    17    B       SOFT    s t        1      0   1    7    0    2    1  ~233~6
 (40)    18    B       SOFT    s t        1      0   1    7    1    2    1  ~233~7
 (39)    19    B       SOFT    s t        1      0   1    4    2    2    1  ~233~8
 (38)    20    B       SOFT    s t        1      0   1    7    1    2    1  ~233~9
 (37)    21    B       SOFT    s t        1      0   1    4    2    2    1  ~233~10
  (7)     4    A       SOFT    s t        2      0   0    7    6    2    0  ~236~1
 (36)    22    B       SOFT    s t        1      0   1    6    0    0    1  ~236~2
  (8)     5    A       SOFT    s t        1      0   1    6    0    0    1  ~236~3
  (9)     6    A       SOFT    s t        1      0   1    6    0    0    1  ~236~4
 (11)     7    A       SOFT    s t        1      0   1    6    0    0    1  ~236~5
 (12)     8    A       SOFT    s t        1      0   1    6    0    0    1  ~236~6
 (17)    12    A       SOFT    s t        1      0   1    6    0    0    1  ~236~7
 (24)    32    B       SOFT    s t        0      0   0    6    2    2    0  ~257~1


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                            d:\isp\seven\seven.rpt
seven

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                             Logic cells placed in LAB 'A'
        +------------------- LC16 |LPM_ADD_SUB:159|addcore:adder|addcore:adder0|gs1
        | +----------------- LC1 |LPM_ADD_SUB:159|addcore:adder|addcore:adder0|result_node2
        | | +--------------- LC2 |LPM_ADD_SUB:194|addcore:adder|addcore:adder0|result_node2
        | | | +------------- LC3 |LPM_ADD_SUB:194|addcore:adder|addcore:adder0|~245~1~3
        | | | | +----------- LC4 ~236~1
        | | | | | +--------- LC5 ~236~3
        | | | | | | +------- LC6 ~236~4
        | | | | | | | +----- LC7 ~236~5
        | | | | | | | | +--- LC8 ~236~6
        | | | | | | | | | +- LC12 ~236~7
        | | | | | | | | | | 
        | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | |   that feed LAB 'A'
LC      | | | | | | | | | | | A B |     Logic cells that feed LAB 'A':
LC16 -> - - * * - - - - - - | * - | <-- |LPM_ADD_SUB:159|addcore:adder|addcore:adder0|gs1
LC3  -> - - * - - - - - - - | * - | <-- |LPM_ADD_SUB:194|addcore:adder|addcore:adder0|~245~1~3
LC5  -> - - - - * - - - - - | * - | <-- ~236~3
LC6  -> - - - - * - - - - - | * - | <-- ~236~4
LC7  -> - - - - * - - - - - | * - | <-- ~236~5
LC8  -> - - - - * - - - - - | * - | <-- ~236~6
LC12 -> - - - - * - - - - - | * - | <-- ~236~7

Pin
4    -> * * - * * - - - - - | * * | <-- A0
11   -> * * - * * * * * * * | * * | <-- A1
9    -> * * - * * * * * * * | * * | <-- A2
8    -> - - * * * * * * * * | * * | <-- A3
7    -> - - * * * * * * * * | * * | <-- A4
6    -> - - * * * * * * * * | * * | <-- A5
5    -> - - - - * * * * * * | * * | <-- A6
LC24 -> - - * - - - - - - - | * - | <-- |LPM_ADD_SUB:194|addcore:adder|addcore:adder0|ps2
LC26 -> - - * - - - - - - - | * - | <-- |LPM_ADD_SUB:194|addcore:adder|addcore:adder0|~245~1~2
LC22 -> - - - - * - - - - - | * - | <-- ~236~2


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                            d:\isp\seven\seven.rpt
seven

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                         Logic cells placed in LAB 'B'
        +------------------------------- LC23 G
        | +----------------------------- LC24 |LPM_ADD_SUB:194|addcore:adder|addcore:adder0|ps2
        | | +--------------------------- LC26 |LPM_ADD_SUB:194|addcore:adder|addcore:adder0|~245~1~2
        | | | +------------------------- LC27 R
        | | | | +----------------------- LC28 ~233~1
        | | | | | +--------------------- LC30 ~233~2
        | | | | | | +------------------- LC31 ~233~3
        | | | | | | | +----------------- LC29 ~233~4
        | | | | | | | | +--------------- LC25 ~233~5
        | | | | | | | | | +------------- LC17 ~233~6
        | | | | | | | | | | +----------- LC18 ~233~7
        | | | | | | | | | | | +--------- LC19 ~233~8
        | | | | | | | | | | | | +------- LC20 ~233~9
        | | | | | | | | | | | | | +----- LC21 ~233~10
        | | | | | | | | | | | | | | +--- LC22 ~236~2
        | | | | | | | | | | | | | | | +- LC32 ~257~1
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC28 -> * - - * - - - - - - - - - - - - | - * | <-- ~233~1
LC30 -> * - - * * - - - - - - - - - - - | - * | <-- ~233~2
LC31 -> * - - * * - - - - - - - - - - - | - * | <-- ~233~3
LC29 -> * - - * * - - - - - - - - - - - | - * | <-- ~233~4
LC25 -> * - - * * - - - - - - - - - - - | - * | <-- ~233~5
LC17 -> * - - * * - - - - - - - - - - - | - * | <-- ~233~6
LC18 -> * - - * * - - - - - - - - - - - | - * | <-- ~233~7
LC19 -> * - - * * - - - - - - - - - - - | - * | <-- ~233~8
LC20 -> * - - * * - - - - - - - - - - - | - * | <-- ~233~9
LC21 -> * - - * * - - - - - - - - - - - | - * | <-- ~233~10
LC32 -> * - - * - - - - - - - - - - - - | - * | <-- ~257~1

Pin
4    -> - - * - * * * * * * * * * - - * | * * | <-- A0
11   -> - - * - * * * * * * * * * - * * | * * | <-- A1
9    -> - - * - * * * * * * * * * - * * | * * | <-- A2
8    -> - * * - * * * * * * * - * * * * | * * | <-- A3
7    -> - * * - * * * * * * * - * * * * | * * | <-- A4
6    -> - * * - * * * * * * * - * * * * | * * | <-- A5
5    -> - - - - - - - - * * * * * * * - | * * | <-- A6
LC1  -> - * - - * * * * - - - * * * - * | - * | <-- |LPM_ADD_SUB:159|addcore:adder|addcore:adder0|result_node2
LC2  -> - - - - * - * - - - * * - * - * | - * | <-- |LPM_ADD_SUB:194|addcore:adder|addcore:adder0|result_node2
LC4  -> * - - * - - - - - - - - - - - - | - * | <-- ~236~1