_primary.vhd

来自「OFDM系统中FFT的Verilog HDL 语言实现。」· VHDL 代码 · 共 22 行

library verilog;
use verilog.vl_types.all;
entity ram is
    port(
        clk             : in     vl_logic;
        addr_a          : in     vl_logic_vector(9 downto 0);
        addr_b          : in     vl_logic_vector(9 downto 0);
        ramina_r        : in     vl_logic_vector(31 downto 0);
        ramina_i        : in     vl_logic_vector(31 downto 0);
        raminb_r        : in     vl_logic_vector(31 downto 0);
        raminb_i        : in     vl_logic_vector(31 downto 0);
        ramouta_r       : out    vl_logic_vector(31 downto 0);
        ramouta_i       : out    vl_logic_vector(31 downto 0);
        ramoutb_r       : out    vl_logic_vector(31 downto 0);
        ramoutb_i       : out    vl_logic_vector(31 downto 0);
        wea             : in     vl_logic;
        web             : in     vl_logic;
        ena             : in     vl_logic;
        enb             : in     vl_logic
    );
end ram;