_primary.vhd

来自「OFDM系统中FFT的Verilog HDL 语言实现。」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity write_addr is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        en              : in     vl_logic;
        count10         : in     vl_logic_vector(3 downto 0);
        read_addr_l     : in     vl_logic_vector(9 downto 0);
        read_addr_h     : in     vl_logic_vector(9 downto 0);
        done            : out    vl_logic;
        write_addr_l    : out    vl_logic_vector(9 downto 0);
        write_addr_h    : out    vl_logic_vector(9 downto 0)
    );
end write_addr;