watch.map.qmsg

可以实现时间调节

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 03 14:39:56 2008 " "Info: Processing started: Wed Dec 03 14:39:56 2008" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off watch -c watch " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off watch -c watch" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "act.vhd 2 1 " "Info: Found 2 design units and 1 entities in source file act.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 act-fun " "Info: Found design unit 1: act-fun" {  } { { "E:/王明/shiyan10/act.vhd" "act-fun" "" { Text "E:/王明/shiyan10/act.vhd" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 act " "Info: Found entity 1: act" {  } { { "E:/王明/shiyan10/act.vhd" "act" "" { Text "E:/王明/shiyan10/act.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "any_even.vhd 2 1 " "Info: Found 2 design units and 1 entities in source file any_even.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 any_even-div1 " "Info: Found design unit 1: any_even-div1" {  } { { "E:/王明/shiyan10/any_even.vhd" "any_even-div1" "" { Text "E:/王明/shiyan10/any_even.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 any_even " "Info: Found entity 1: any_even" {  } { { "E:/王明/shiyan10/any_even.vhd" "any_even" "" { Text "E:/王明/shiyan10/any_even.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "minute.vhd 2 1 " "Info: Found 2 design units and 1 entities in source file minute.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 minute-fun " "Info: Found design unit 1: minute-fun" {  } { { "E:/王明/shiyan10/minute.vhd" "minute-fun" "" { Text "E:/王明/shiyan10/minute.vhd" 15 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 minute " "Info: Found entity 1: minute" {  } { { "E:/王明/shiyan10/minute.vhd" "minute" "" { Text "E:/王明/shiyan10/minute.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "msecond.vhd 2 1 " "Info: Found 2 design units and 1 entities in source file msecond.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 msecond-fun " "Info: Found design unit 1: msecond-fun" {  } { { "E:/王明/shiyan10/msecond.vhd" "msecond-fun" "" { Text "E:/王明/shiyan10/msecond.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 msecond " "Info: Found entity 1: msecond" {  } { { "E:/王明/shiyan10/msecond.vhd" "msecond" "" { Text "E:/王明/shiyan10/msecond.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "second.vhd 2 1 " "Info: Found 2 design units and 1 entities in source file second.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 second-fun " "Info: Found design unit 1: second-fun" {  } { { "E:/王明/shiyan10/second.vhd" "second-fun" "" { Text "E:/王明/shiyan10/second.vhd" 15 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 second " "Info: Found entity 1: second" {  } { { "E:/王明/shiyan10/second.vhd" "second" "" { Text "E:/王明/shiyan10/second.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "watch.vhd 2 1 " "Info: Found 2 design units and 1 entities in source file watch.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 watch-behave " "Info: Found design unit 1: watch-behave" {  } { { "E:/王明/shiyan10/watch.vhd" "watch-behave" "" { Text "E:/王明/shiyan10/watch.vhd" 21 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 watch " "Info: Found entity 1: watch" {  } { { "E:/王明/shiyan10/watch.vhd" "watch" "" { Text "E:/王明/shiyan10/watch.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "set_clk minute.vhd(53) " "Warning: VHDL Process Statement warning at minute.vhd(53): signal set_clk is in statement, but is not in sensitivity list" {  } { { "E:/vdhl试验/watch/minute.vhd" "" "" { Text "E:/vdhl试验/watch/minute.vhd" 53 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "set_hour minute.vhd(72) " "Warning: VHDL Process Statement warning at minute.vhd(72): signal set_hour is in statement, but is not in sensitivity list" {  } { { "E:/vdhl试验/watch/minute.vhd" "" "" { Text "E:/vdhl试验/watch/minute.vhd" 72 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "any_even:u1\|coutQ\[0\]~0 24 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=24) from the following logic: any_even:u1\|coutQ\[0\]~0" {  } { { "e:/vdhl试验/watch/any_even.vhd" "" "coutQ\[0\]~0" { Text "e:/vdhl试验/watch/any_even.vhd" 20 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "c:/quartus/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "c:/quartus/libraries/megafunctions/lpm_counter.tdf" 221 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "alt_counter_f10ke" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 256 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "c:/quartus/libraries/megafunctions/lpm_add_sub.tdf" "lpm_add_sub" "" { Text "c:/quartus/libraries/megafunctions/lpm_add_sub.tdf" 103 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "c:/quartus/libraries/megafunctions/addcore.tdf" "addcore" "" { Text "c:/quartus/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "a_csnbuffer" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "c:/quartus/libraries/megafunctions/altshift.tdf" "altshift" "" { Text "c:/quartus/libraries/megafunctions/altshift.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "308 " "Info: Implemented 308 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "284 " "Info: Implemented 284 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 03 14:40:04 2008 " "Info: Processing ended: Wed Dec 03 14:40:04 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0}  } {  } 0}