segment.vhd

用VHDL编写的计算器：能实现简单的加减乘除四则运算

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:04:02 11/17/2006 
-- Design Name: 
-- Module Name:    segment - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity segment is
    Port ( clk : in  STD_LOGIC;
			 row : in  STD_LOGIC_VECTOR (1 downto 0);
			 key:in std_logic_vector(7 downto 0);
           num : in  STD_LOGIC_VECTOR (15 downto 0);
			  dot :in std_logic;
           com : out  STD_LOGIC_VECTOR (3 downto 0);
           cs : out  STD_LOGIC;
           d : out  STD_LOGIC_VECTOR (7 downto 0));
end segment;

architecture Behavioral of segment is
signal scanclk:std_logic_vector(1 downto 0);
signal scan:std_logic_vector(27 downto 0);
signal seg1,seg2,seg3,seg4,seg:std_logic_vector(7 downto 0);

begin

process(clk)
begin
 if rising_edge(clk)then
 scan<=scan+'1';
 end if;
 scanclk<=scan(8 downto 7);
 end process;
 process(row)
 begin
 if row="01"or row="10"  then

  cs<='0';
 d<=key;
 else
 cs<='1';
 d<=seg;
 end if;
end process;
process(scanclk)
begin
case scanclk is
when"00"=>
--com<="1110";
com<="0001";
seg<=seg1;
when"01"=>
--com<="1101";
com<="0010";
seg<=seg2(7 downto 5)&dot&seg2(3 downto 0);
when"10"=>
--com<="1011";
com<="0100";
seg<=seg3;
when"11"=>
--com<="0111";
com<="1000";
seg<=seg4;
when others=>
--com<="1111";
com<="0000";
seg<="11111111";
end case;

end process;

  

process(num)
  begin
  case num(3 downto 0) is
    when"0000"=>seg1<="00010001";
	 when"0001"=>seg1<="11010111";
	 when"0010"=>seg1<="00110010";
	 when"0011"=>seg1<="10010010";
	 when"0100"=>seg1<="11010100";
	 when"0101"=>seg1<="10011000";
	 when"0110"=>seg1<="00011000";
	 when"0111"=>seg1<="11010011";
	 when"1000"=>seg1<="00010000";
	 when"1001"=>seg1<="10010000";
	when others=>seg1<="11101111";
  end case;
 end process;
 process(num)
  begin
  case num(7 downto 4) is
    when"0000"=>seg2<="00010001";
	 when"0001"=>seg2<="11010111";
	 when"0010"=>seg2<="00110010";
	 when"0011"=>seg2<="10010010";
	 when"0100"=>seg2<="11010100";
	 when"0101"=>seg2<="10011000";
	 when"0110"=>seg2<="00011000";
	 when"0111"=>seg2<="11010011";
	 when"1000"=>seg2<="00010000";
	 when"1001"=>seg2<="10010000";
	 when others=>seg2<="11101111";
  end case;
 end process;
 process(num)
 begin
   if num(11 downto 8)="1011"then
	seg3<="11111110";
	else
	seg3<="11111111";
	end if;
 end process;
 process(num)
  begin
  case num(15 downto 12) is

 when"1010"=>seg4<="11010110";
	 when"1011"=>seg4<="11111110";
	when"1100"=>seg4<="01010100";
 when"1101"=>seg4<="10111010";
	when others=>seg4<="11111111";
  end case;
 end process;



end Behavioral;