fadd4.vhd

用VHDL编写的计算器：能实现简单的加减乘除四则运算

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:55:44 11/09/2006 
-- Design Name: 
-- Module Name:    fadd4 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
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-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
--fadd4.vhd 4-bit ripple-carry adder
library ieee ;
use ieee.std_logic_1164.all;
--use work.components.all;
entity fadd4 is
port(
  	a	: in std_logic_vector(3 downto 0);--???
	b 	: in std_logic_vector(3 downto 0);--??
  	ci 	: in std_logic;--????
  	co 	: out std_logic;--????
  	sum : out std_logic_vector(3 downto 0));--?
end fadd4;
architecture behavior of fadd4 is 
component fadd is

port(
  a: in std_logic;
  b: in std_logic;
  ci : in std_logic;
  co: out std_logic; 
  sum : out std_logic);

end component;
  signal ci_ns : std_logic_vector(2 downto 0);--ci?co???
begin 
  u0: fadd  port map (a(0),b(0),ci,ci_ns(0),sum(0));
  u1: fadd  port map (a(1),b(1),ci_ns(0),ci_ns(1),sum(1));
  u2: fadd  port map (a(2),b(2),ci_ns(1),ci_ns(2),sum(2));
  u3: fadd  port map (a(3),b(3),ci_ns(2),co,sum(3));
end behavior;