mul.vhd

用VHDL编写的计算器：能实现简单的加减乘除四则运算

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-- Company: 
-- Engineer: 
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-- Create Date:    11:37:47 11/24/2006 
-- Design Name: 
-- Module Name:    mul - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
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-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mul is
    Port ( num1 : in  STD_LOGIC_VECTOR (3 downto 0);
           num2 : in  STD_LOGIC_VECTOR (3 downto 0);
           num : out  STD_LOGIC_VECTOR (7 downto 0));
end mul;

architecture Behavioral of mul is
signal q1,q2:integer range 0 to 9;
signal q3,q:integer range 0 to 200;
begin
q1<=conv_integer(num1);
q2<=conv_integer(num2);
q3<=q1*q2;
num<=conv_std_logic_vector(q,8);
process(q3)
begin
if q3<10 then
q<=q3;
elsif q3>=10 and q3<20 then
q<=q3+6;
elsif q3>=20 and q3<30 then
q<=q3+12;
elsif q3>=30 and q3<40 then
q<=q3+18;
elsif q3>=40 and q3<50 then
q<=q3+24;
elsif q3>=50 and q3<60 then
q<=q3+30;
elsif q3>=60 and q3<70 then
q<=q3+36;
elsif q3>=70 and q3<80 then
q<=q3+42;
elsif q3>=80 and q3<90 then
q<=q3+48;
end if;
end process;


end Behavioral;