sign.vhd

用VHDL编写的计算器：能实现简单的加减乘除四则运算

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:29:31 11/21/2006 
-- Design Name: 
-- Module Name:    add - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sign is
    Port ( clk : in  STD_LOGIC;
           clr : in  STD_LOGIC;
           nums : in  STD_LOGIC;
           adds : in  STD_LOGIC;
           subs : in  STD_LOGIC;
           muls : in  STD_LOGIC;
           divs : in  STD_LOGIC;
			  signs:in std_logic;
			  equals:in std_logic;
			  num : in  STD_LOGIC_VECTOR (3 downto 0);
			  dot:out std_logic;
           d:out std_logic_vector(15 downto 0)
			  );
end sign;

architecture Behavioral of sign is
component add is
    Port ( clk:in std_logic;
	        start:in std_logic;
           num1 : in  STD_LOGIC_VECTOR (3 downto 0);
           num2 : in  STD_LOGIC_VECTOR (3 downto 0);
           num : out  STD_LOGIC_VECTOR (7 downto 0));
end component;
component sub is
    Port ( num1 : in  STD_LOGIC_VECTOR (3 downto 0);
           num2 : in  STD_LOGIC_VECTOR (3 downto 0);
           num : out  STD_LOGIC_VECTOR (7 downto 0));
end component;
component mul is
    Port ( num1 : in  STD_LOGIC_VECTOR (3 downto 0);
           num2 : in  STD_LOGIC_VECTOR (3 downto 0);
           num : out  STD_LOGIC_VECTOR (7 downto 0));
end component;
component div is
    Port ( clk : in  STD_LOGIC;
           num1 : in  STD_LOGIC_VECTOR (3 downto 0);
           num2 : in  STD_LOGIC_VECTOR (3 downto 0);
           num : out  STD_LOGIC_VECTOR (7 downto 0));
end component;
--type states is(idle,wait1,wait2,sadd,ssub,smul,sdiv,wait3,wait4,scal);

--signal state,next_state:states;
signal s :  STD_LOGIC_VECTOR (1 downto 0);
signal p1,p,p2:   STD_LOGIC_VECTOR (1 downto 0):="00";
signal num1,q1 ,q3,q4:   STD_LOGIC_VECTOR (3 downto 0):="0000";
signal num2,q2,num3 :   STD_LOGIC_VECTOR (3 downto 0):="0000";
signal flag:std_logic:='0';
signal d1,d2,d3,d4:std_logic_vector(7 downto 0);
signal d5:std_logic_vector(7 downto 0):="00000000";
signal start,z,s1,s2,s3,sign1:std_logic:='0';
signal dots:std_logic;
signal n,n1,n2:integer:=0;

begin
process(nums,num,clk,clr)
begin
if clr='1' then
--num1<="0000";
num3<="0000";
  elsif falling_edge(clk)then
   if nums='1' then
	 num3<=num;
	 --num1<=num2;
	 end if;
end if;
  end process;
  process(clk,clr,adds,subs,muls,divs,num3)
  begin
    if clr='1' then
	 num1<="0000";
	 elsif falling_edge(clk)then
	    if adds='1' or subs='1' or muls='1' or divs='1'  then
		 num1<=num3;
		 end if;
	 end if;
	 end process;
process(clk,signs,nums,clr)
begin
 if clr='1' then
 d(11 downto 8)<="1111";
 elsif rising_edge(clk)then
   if signs='1' or sign1='1' then
	d(11 downto 8)<="1011";
	elsif equals='1' or nums='1'  then
	d(11 downto 8)<="1111";
	end if;
 end if;
 end process;
 process(clk,clr,adds,subs,muls,divs)
 begin
    if clr='1' then
	 d(15 downto 12)<="1111";
	 elsif rising_edge(clk)then
	   if adds='1' then
		d(15 downto 12)<="1010";
		elsif subs='1' then
		d(15 downto 12 )<="1011";
		elsif muls='1' then
		d(15 downto 12)<="1100";
		elsif divs='1' then
		d(15 downto 12)<="1101";
		end if;
	 end if;
end process;
	 
	 

  process(clk,clr,equals,num3)
  begin
    if clr='1' then
	 flag<='0';
	 num2<="0000";
	 elsif falling_edge(clk)then
	    if equals='1' then
		 flag<='1'; 
		 num2<=num3;
		 end if;
	 end if;
	 end process;
	-- process(clk,clr,signs)
	--  begin
 --   if clr='1' then
	-- s2<='0';
	-- s3<='0';
	-- elsif falling_edge(clk)then
	  --  if signs='1' and s4='1' then
	--	 s2<='1'; 
	--	 elsif signs='1' and s5='1' then
		-- s3<='1';
	--	 end if;
	-- end if;
	 --end process;
process(clk,clr,nums)
begin
  if clr='1' or nums='1' then
  n<=0;
  elsif rising_edge(clk)then
     if signs='1' then
	  n<=n+1;
	  end if;
	end if;
end process;
process(clr,clk,adds,subs,muls,divs,equals,n)
begin
   if clr='1' then
	n1<=0;
	n2<=0;
	elsif rising_edge(clk)then
	  if (adds='1' or subs='1' or muls='1' or divs='1')then
	  n1<=n;
	  elsif equals='1' then
	  n2<=n;
	  end if;
	 end if;
 end process;
 process(n1,n2)
 begin
   if n1>0 then
	s2<='1';
	else
	s2<='0';
	end if;
	if n2>0 then
	s3<='1';
	else
	s3<='0';
	end if;
end process;
  
	 
	 process(clk,clr,adds,subs,muls,divs,clk)
	 begin
	   if clr='1' then
		p2<="00";
		elsif rising_edge(clk)then
	     if adds='1' then
				
				 p2<="00";
				 
				 
				
				 elsif subs='1' then
				 
				 p2<="01";
			
				
				 elsif muls='1' then
				
				 p2<="10";
				 elsif divs='1' then
			
				 p2<="11";
				 end if;
			end if;
			end process;
			process(start,num1,num2,p2,s2,s3)
 begin
  if start='0' then
 sign1<='0';
  elsif start='1' then
	if p2="00"then
	  if (s2='0' and s3='0')then
	  sign1<='0';
	  elsif (s2='1' and s3='1')  then
	  sign1<='1';
	  elsif (s2='0' and s3='1')then
	    if num1>num2 then
	    sign1<='0';
	    else
	    sign1<='1';
	    end if;
	  elsif (s2='1' and s3='0')then
	   if num1>num2 then
	    sign1<='1';
	    else
	    sign1<='0';
	    end if;
	  end if;
	elsif p2="01" then
	  	if (s2='0' and s3='1')then
	  sign1<='0';
	  elsif (s2='1' and s3='0')  then
	  sign1<='1';
	  elsif (s2='0' and s3='0')then
	    if num1>num2 then
	    sign1<='0';
	    else
	    sign1<='1';
	    end if;
	  elsif (s2='1' and s3='1')then
	   if num1>num2 then
	    sign1<='1';
	    else
	    sign1<='0';
	    end if;
	  end if;
	elsif p2="10" or p2="11"then
	  if (s2='0' and s3='0')or (s2='1' and s3='1')  then
	  sign1<='0';
	  else
	  sign1<='1';
	  end if;
  end if;
  end if;
 end process;
 
process(z,num3,d1,p2,s2,s3)
 begin
  if z='0' then
 d(7 downto 0)<="0000"&num3;
  elsif z='1' then
	if p2="00"then
	  if (s2='0' and s3='0')or (s2='1' and s3='1')  then
	  d(7 downto 0)<=d1;
	  else
	  d(7 downto 0)<=d2;
	  end if;
	elsif p2="01" then
	  if (s2='0' and s3='0')or (s2='1' and s3='1') then
     d(7 downto 0)<=d2;
	  else
	  d(7 downto 0)<=d1;
	  end if;
	elsif p2="10"then
	  d(7 downto 0)<=d3;
	elsif p2="11"then
	d(7 downto 0)<=d4;
   end if;
  end if;
 end process;

				
process(clk,flag,clr)
variable cnt:integer ;
begin
if clr='1'  then
cnt:=0;
elsif rising_edge(clk)then
   if flag='1' then
	cnt:=cnt+1;
	end if;
end if;
if cnt>=500 then
    start<='1' ;
    else
    start<='0';
end if;
  if cnt>=700 then
  z<='1';
  else
  z<='0';
  end if;
end process;

process(clk,clr,divs)
begin
if clr='1' then
dots<='1';
elsif rising_edge(clk)then
  if divs='1' then
  dots<='0';
  end if;
end if;
end process;
dot<=dots or (not z);
     
u1:add port map (clk,start,num1,num2,d1);
u2:sub port map(num1,num2,d2);
u3:mul port map(num1,num2,d3);
u4: div port map(clk,num1,num2,d4);	
end Behavioral;