key_ctrl.vhd

用VHDL编写的计算器：能实现简单的加减乘除四则运算

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:53:48 10/26/2006 
-- Design Name: 
-- Module Name:    key_scan - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity key_ctrl is
    Port ( clk : in  STD_LOGIC;
           key : out  STD_LOGIC_VECTOR (7 downto 0);
           row : in  STD_LOGIC_VECTOR (1 downto 0);
			  num:out std_logic_vector(3 downto 0);
			  nums:out std_logic;
			  adds:out std_logic;
			  subs:out std_logic;
			  muls:out std_logic;
			  divs:out std_logic;
			  equals:out std_logic;
			  signs:out std_logic;
			  clr:out std_logic
			  --mode_sel:out std_logic;
			  --key_valid:out std_logic
			  );
           
end key_ctrl;

architecture Behavioral of key_ctrl is
  signal num1,num2:std_logic_vector(3 downto 0);
  signal key_pressed,clk1kh,start,clk1:std_logic;
  signal scan_cnt:std_logic_vector(3 downto 0):="0000";
  signal mode_sels,key_valids:std_logic:='0';
  --signal num,add_pos,sub_neg,mul,div,equal_clr,mode,key_valid:std_logic;
  --signal q:std_logic_vector(9 downto 0);
  signal clr1,equals1,en,adds1,subs1,muls1,divs1,signs1,nums1:std_logic:='0';
begin
--key_valid<=key_valids;
process(clk)
variable cnt:integer range 0 to 499:=0;
begin
  if rising_edge(clk)then
   if cnt=499 then
	cnt:=0;
	else
	cnt:=cnt+1;
	end if;
	
	if(cnt=499)then
	clk1kh<='1';
	else
	clk1kh<='0';
	end if;
  end if;
end process;
  


process(clk,clk1kh,key_pressed)
begin
  if falling_edge(clk)then
    if(key_pressed='1' and clk1kh='1')then
	 scan_cnt<=scan_cnt+'1';
	 end if;
  end if;
end process;


   
   key<="11111110" when scan_cnt(2 downto 0)="000"else
        "11111101" when scan_cnt(2 downto 0)="001"else
		  "11111011" when scan_cnt(2 downto 0)="010"else
		  "11110111" when scan_cnt(2 downto 0)="011"else
		  "11101111" when scan_cnt(2 downto 0)="100"else
		  "11011111" when scan_cnt(2 downto 0)="101"else
		  "10111111" when scan_cnt(2 downto 0)="110"else
		  "01111111";
	key_pressed<=row(0) when scan_cnt(3)='0' else
	             row(1);


process(clk)
variable cnt:integer range 0 to 3:=0;
begin
   if rising_edge(clk)then
	  if cnt=3 then
	  clk1<=not clk1;
	  cnt:=0;
	  else
	  cnt:=cnt+1;
	  end if;
	end if;
end process;
process(clk1kh,clk,key_pressed)
variable cnt:integer;
begin

  if key_pressed='1' then
  cnt:=500;
  elsif falling_edge(clk)then
    --if(clk1kh='1')then
	   if cnt/=0 then
	   cnt:=cnt-1;
	   end if;
   -- end if;
  end if;
    if cnt=1 then
	 key_valids<='1';
   else
	 key_valids<='0';
	 end if; 
	
	end process;

process(clk1kh,key_valids)
variable cnt:integer range 0 to 2000:=2000;
begin
  if key_valids='1' then
  cnt:=0;
  elsif  rising_edge(clk1kh) then
    if cnt=2000 then
	 cnt:=2000;
	 else 
	 cnt:=cnt+1;
	 end if;
  end if;
  if cnt=1599 then
  start<='1';
  else
  start<='0';
  end if;
end process;
	



process(clk,scan_cnt)
begin
  if rising_edge(clk) then
  
    case scan_cnt is
	 
	 when"0000"=>
	 num1<="0000";

	 when"0001"=>
	 num1<="0001";
	 when"0010"=>
	 num1<="0010";
	 when"0011"=>
	 num1<="0011";
	 when"0100"=>
	 num1<="0100";
	 when"0101"=>
	 num1<="0101";
	 when"0110"=>
	 num1<="0110";
	 when"0111"=>
	 num1<="0111";
	 when"1000"=>
	 num1<="1000";
	 when"1001"=>
	 num1<="1001";
	 when"1010"=>
	 num1<="1010";--- +/+
	 when"1011"=>
	 num1<="1011";--- -/-
	 when"1100"=>
	 num1<="1100";--- *
	 
	 when"1101"=>
	 num1<="1101";---- /
	 when"1110"=>
	 num1<="1110";--- =/clear
	 when"1111"=>
	 num1<="1111";---  mode
	-- mode_sels<='1';
	 when others=>
	 num1<="1111";
    --mode_sels<='0';
	 end case;
	 
  end if;
end process;
--mode_sel<=mode_sels and key_valids ;
process(clk,key_valids,num1)
begin
  if rising_edge(clk) then
   if key_valids='1' then
    case num1 is
	 when"0000"=>
	 num2<="0000";

	 when"0001"=>
	 num2<="0001";
	 when"0010"=>
	 num2<="0010";
	 when"0011"=>
	 num2<="0011";
	 when"0100"=>
	 num2<="0100";
	 when"0101"=>
	 num2<="0101";
	 when"0110"=>
	 num2<="0110";
	 when"0111"=>
	 num2<="0111";
	 when"1000"=>
	 num2<="1000";
	 when"1001"=>
	 num2<="1001";
	 when"1010"=>
	 num2<="1010";--- +/+
	 when"1011"=>
	 num2<="1011";--- -/-
	 when"1100"=>
	 num2<="1100";--- *
	 when"1101"=>
	 num2<="1101";---- /
	 when"1110"=>
	 num2<="1110";--- =/clear
	 when"1111"=>
	 num2<="1111";---  mode
	-- mode_sels<='1';
	 when others=>
	 num2<="1111";
    --mode_sels<='0';
	 end case;
  end if;
  end if;
end process;
process(key_valids,num2)
 begin
 if  key_valids='1' then
  
    if num2>="0000" and num2<="1000" then
	 nums1<='1';
	 else
	 nums1<='0';
	 end if;
	 if num2="1001"then
	 signs1<='1';
	 else
	 signs1<='0';
	 end if;
    if num2="1010" then
	  adds1<='1';
	 else
	  adds1<='0';
	 end if;
    if num2="1011" then
	 subs1<='1';
	 else
	 subs1<='0';
	 end if;	 
	 if num2="1100" then
	muls1<='1';
	 else
	 muls1<='0';
	 end if;
	 if num2="1111" then
	 divs1<='1';
	 else
	 divs1<='0';
	 end if;
	
	 if num2="1110" then
	 equals1<='1';
	 else
	 equals1<='0';
	 end if;
	 if num2="1101" then
	 clr1<='1';
	 else
	 clr1<='0';
	 end if;
  end if;
end process;
process(clk,equals1,clr1)
begin
	   if clr1='1' then
		en<='0';
   elsif rising_edge(clk)then

		if equals1='1' then
		en<='1';
		end if;
	end if;
end process;
clr<=clr1;
equals<=equals1;
process(en,num2,adds1,subs1,muls1,divs1,signs1)
begin
if en='0' then
num<=num2;
adds<=adds1;
subs<=subs1;
muls<=muls1;
divs<=divs1;
nums<=nums1;
signs<=signs1;
end if;
end process;
end Behavioral;


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