top.vhd

用VHDL编写的计算器：能实现简单的加减乘除四则运算

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:19:03 11/21/2006 
-- Design Name: 
-- Module Name:    top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
    Port ( clk : in  STD_LOGIC;
	        row:in std_logic_vector(1 downto 0);
           cs : out  STD_LOGIC;
           com : out  STD_LOGIC_VECTOR (3 downto 0);
           d : out  STD_LOGIC_VECTOR (7 downto 0));
end top;

architecture Behavioral of top is

component add is
    Port ( num1 : in  STD_LOGIC_VECTOR (3 downto 0);
           num2 : in  STD_LOGIC_VECTOR (3 downto 0);
           num : out  STD_LOGIC_VECTOR (7 downto 0)
			 );
end component;
component segment is
    Port ( clk : in  STD_LOGIC;
			  row : in  STD_LOGIC_VECTOR (1 downto 0);
			  key:in std_logic_vector(7 downto 0);
           num : in  STD_LOGIC_VECTOR (15 downto 0);
			  dot :in std_logic;
           com : out  STD_LOGIC_VECTOR (3 downto 0);
           cs : out  STD_LOGIC;
           d : out  STD_LOGIC_VECTOR (7 downto 0));
end component;
component key_ctrl is
    Port ( clk : in  STD_LOGIC;
           key : out  STD_LOGIC_VECTOR (7 downto 0);
           row : in  STD_LOGIC_VECTOR (1 downto 0);
			  num:out std_logic_vector(3 downto 0);
			  nums:out std_logic;
			  adds:out std_logic;
			  subs:out std_logic;
			  muls:out std_logic;
			  divs:out std_logic;
			  equals:out std_logic;
			  signs:out std_logic;
			  clr:out std_logic
			  );
           
end component;
component sign is
    Port ( clk : in  STD_LOGIC;
           clr : in  STD_LOGIC;
           nums : in  STD_LOGIC;
           adds : in  STD_LOGIC;
           subs : in  STD_LOGIC;
           muls : in  STD_LOGIC;
           divs : in  STD_LOGIC;
			  signs:in std_logic;
			  equals:in std_logic;
			  num : in  STD_LOGIC_VECTOR (3 downto 0);
			  dot:out std_logic;
           d:out std_logic_vector(15 downto 0)
			  );
end component;
signal num1,num,num2:std_logic_vector(3 downto 0);
signal co,signed,clk1:std_logic;
signal key,q1:std_logic_vector(7 downto 0);
signal clr,equals,nums,adds,subs,muls,divs,signs:std_logic;
signal q:std_logic_vector(15 downto 0);
signal dot:std_logic;
begin
q1<="0000"&num;
u2:segment port map(clk,row,key,q,dot,com,cs,d);
u3:key_ctrl port map(clk,key,row,num,nums,adds,subs,muls,divs,equals,signs,clr);
u4:sign port map(clk,clr,nums,adds,subs,muls,divs,signs,equals,num,dot,q);
end Behavioral;