add.vhd

来自「用VHDL编写的计算器：能实现简单的加减乘除四则运算」· VHDL 代码 · 共 73 行

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:29:31 11/21/2006 
-- Design Name: 
-- Module Name:    add - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity add is
    Port ( clk:in std_logic;
	        start:in std_logic;
	        num1 : in  STD_LOGIC_VECTOR (3 downto 0);
           num2 : in  STD_LOGIC_VECTOR (3 downto 0);
           num : out  STD_LOGIC_VECTOR (7 downto 0));
end add;


architecture Behavioral of add is
signal q1,q2:integer range 0 to 9;
signal q3:integer range 0 to 18;
signal q:integer range 0 to 24;
begin
q1<=conv_integer(num1);
q2<=conv_integer(num2);
num<=conv_std_logic_vector(q,8);
--process(clk,start,q1,q2)
--begin
  --if rising_edge(clk)then
   --  if start='1' then


q3<=q1+q2;

 -- end if;
-- end if;
 --end process;
process(q3)
begin
--if rising_edge(clk)then
if q3>=10 then
q<=q3+6;
else
q<=q3;
end if;
--end if;
end process;



end Behavioral;