sub.vhd

用VHDL编写的计算器：能实现简单的加减乘除四则运算

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:41:55 11/21/2006 
-- Design Name: 
-- Module Name:    sub - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sub is
    Port ( num1 : in  STD_LOGIC_VECTOR (3 downto 0);
           num2 : in  STD_LOGIC_VECTOR (3 downto 0);
           num : out  STD_LOGIC_VECTOR (7 downto 0));
end sub;

architecture Behavioral of sub is
signal q1,q2:integer range 0 to 9;

signal q:integer range 0 to 9;
begin
q1<=conv_integer(num1);
q2<=conv_integer(num2);
process(q1,q2)
begin
if q1>=q2 then
q<=q1-q2;
else
q<=q2-q1;
end if;
end process;
num<=conv_std_logic_vector(q,8);

end Behavioral;