fadd.vhd

用VHDL编写的计算器：能实现简单的加减乘除四则运算

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-- Company: 
-- Engineer: 
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-- Create Date:    22:12:45 11/09/2006 
-- Design Name: 
-- Module Name:    fadd - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
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-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fadd is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           ci : in  STD_LOGIC;
           co : out  STD_LOGIC;
           sum : out  STD_LOGIC);
end fadd;

architecture Behavioral of fadd is

begin

  co<=(a and b) or (b and ci) or (a and ci);
  sum<=a xor b xor ci;
end Behavioral;