div.vhd

用VHDL编写的计算器：能实现简单的加减乘除四则运算

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:08:31 11/16/2006 
-- Design Name: 
-- Module Name:    div - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity div is
    Port ( clk : in  STD_LOGIC;
           num1 : in  STD_LOGIC_VECTOR (3 downto 0);
           num2 : in  STD_LOGIC_VECTOR (3 downto 0);
           num : out  STD_LOGIC_VECTOR (7 downto 0));
end div;

architecture Behavioral of div is
component mul2 is
    Port ( num1 : in  STD_LOGIC_VECTOR (3 downto 0);
           num2 : in  STD_LOGIC_VECTOR (8 downto 0);
         --  start : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           num : out  STD_LOGIC_VECTOR (11 downto 0));
end component;
component add1 is
    Port ( num1 : in  STD_LOGIC_VECTOR (3 downto 0);
           num2 : in  STD_LOGIC_VECTOR (3 downto 0);
           num : out  STD_LOGIC_VECTOR (7 downto 0);
           cout : out STD_LOGIC
			 );
end component;

signal q:std_logic_vector(8 downto 0);
signal d:std_logic_vector(11 downto 0);
signal n:std_logic_vector(3 downto 0);
signal ci,co:std_logic;
signal q1,q2:STD_LOGIC_VECTOR(3 DOWNTO 0);
signal q3:std_logic_vector(7 downto 0);
begin
q2<="000"&ci;q1<=d(11 downto 8);
u1:mul2 port map(num1,q,clk,d);
u2:add1 port map(q1,q2,q3,co);
num<=q3(3 downto 0)&n;
process(num2)
begin
  case num2 is
  when"0001"=>
  q<="100000000";
  when"0010"=>
  q<="010000000";
  when"0011"=>
  q<="001010101";
  when"0100"=>
  q<="001000000";
  when"0101"=>
  q<="000110011";
  when"0110"=>
  q<="000101010";
  when"0111"=>
  q<="000100100";
  when"1000"=>
  q<="000100000";
  when"1001"=>
  q<="000011100";
  when others=>
  q<="000000000";
  end case;
 end process;
process(d)
begin
 case d(7 downto 4)is
 when"0000"=>n<="0000";
 when"0001"=>n<="0001";
 when"0010"=>
   if d(3)='1' then
   n<="0010";
   else
   n<="0001";
	end if;
 when"0011"=>n<="0010";
 when"0100"=>n<="0011";
 when"0101"=>
   if d(3 downto 2)="11"then
	n<="0100";
	else
	n<="0011";
	end if;
 when"0110"=>n<="0100";
 when"0111"=>
 if d(3)='1' then
   n<="0101";
   else
   n<="0100";
	end if;
 when"1000"=>n<="0101";
 when"1001"=>n<="0110";
 when"1010"=>
  if d(3)='1' then
   n<="0111";
   else
   n<="0110";
	end if;
 
 when"1011"=>n<="0111";
 when"1100"=>n<="1000";
 when"1101"=>n<="1000";
  if d(3 downto 2)="11"then
	n<="1001";
	else
	n<="1000";
	end if;
 when"1110"=>n<="1001";
 when"1111"=>
   if d(3 downto 2)="00" then
	n<="1001";
	else
	n<="0000";
	end if;
 when others=>n<="1111";
 end case;
end process;
process(d)
begin
  if d(7 downto 2)="111101" or
  d(7 downto 2)="111110" or
  d(7 downto 2)="111111"  then
  ci<='1';
  else
  ci<='0';
  end if;
end process;

end Behavioral;