dds_new.hier_info

来自「驱动时钟加入了PLL,使得DDS的驱动时钟可变.32位的NCO使得DDS的分辨率」· HIER_INFO 代码 · 共 1,590 行 · 第 1/4 页

address_a[5] => ram_block1a41.PORTAADDR5
address_a[5] => ram_block1a42.PORTAADDR5
address_a[5] => ram_block1a43.PORTAADDR5
address_a[5] => ram_block1a44.PORTAADDR5
address_a[5] => ram_block1a45.PORTAADDR5
address_a[5] => ram_block1a46.PORTAADDR5
address_a[5] => ram_block1a47.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[6] => ram_block1a16.PORTAADDR6
address_a[6] => ram_block1a17.PORTAADDR6
address_a[6] => ram_block1a18.PORTAADDR6
address_a[6] => ram_block1a19.PORTAADDR6
address_a[6] => ram_block1a20.PORTAADDR6
address_a[6] => ram_block1a21.PORTAADDR6
address_a[6] => ram_block1a22.PORTAADDR6
address_a[6] => ram_block1a23.PORTAADDR6
address_a[6] => ram_block1a24.PORTAADDR6
address_a[6] => ram_block1a25.PORTAADDR6
address_a[6] => ram_block1a26.PORTAADDR6
address_a[6] => ram_block1a27.PORTAADDR6
address_a[6] => ram_block1a28.PORTAADDR6
address_a[6] => ram_block1a29.PORTAADDR6
address_a[6] => ram_block1a30.PORTAADDR6
address_a[6] => ram_block1a31.PORTAADDR6
address_a[6] => ram_block1a32.PORTAADDR6
address_a[6] => ram_block1a33.PORTAADDR6
address_a[6] => ram_block1a34.PORTAADDR6
address_a[6] => ram_block1a35.PORTAADDR6
address_a[6] => ram_block1a36.PORTAADDR6
address_a[6] => ram_block1a37.PORTAADDR6
address_a[6] => ram_block1a38.PORTAADDR6
address_a[6] => ram_block1a39.PORTAADDR6
address_a[6] => ram_block1a40.PORTAADDR6
address_a[6] => ram_block1a41.PORTAADDR6
address_a[6] => ram_block1a42.PORTAADDR6
address_a[6] => ram_block1a43.PORTAADDR6
address_a[6] => ram_block1a44.PORTAADDR6
address_a[6] => ram_block1a45.PORTAADDR6
address_a[6] => ram_block1a46.PORTAADDR6
address_a[6] => ram_block1a47.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.PORTAADDR7
address_a[7] => ram_block1a15.PORTAADDR7
address_a[7] => ram_block1a16.PORTAADDR7
address_a[7] => ram_block1a17.PORTAADDR7
address_a[7] => ram_block1a18.PORTAADDR7
address_a[7] => ram_block1a19.PORTAADDR7
address_a[7] => ram_block1a20.PORTAADDR7
address_a[7] => ram_block1a21.PORTAADDR7
address_a[7] => ram_block1a22.PORTAADDR7
address_a[7] => ram_block1a23.PORTAADDR7
address_a[7] => ram_block1a24.PORTAADDR7
address_a[7] => ram_block1a25.PORTAADDR7
address_a[7] => ram_block1a26.PORTAADDR7
address_a[7] => ram_block1a27.PORTAADDR7
address_a[7] => ram_block1a28.PORTAADDR7
address_a[7] => ram_block1a29.PORTAADDR7
address_a[7] => ram_block1a30.PORTAADDR7
address_a[7] => ram_block1a31.PORTAADDR7
address_a[7] => ram_block1a32.PORTAADDR7
address_a[7] => ram_block1a33.PORTAADDR7
address_a[7] => ram_block1a34.PORTAADDR7
address_a[7] => ram_block1a35.PORTAADDR7
address_a[7] => ram_block1a36.PORTAADDR7
address_a[7] => ram_block1a37.PORTAADDR7
address_a[7] => ram_block1a38.PORTAADDR7
address_a[7] => ram_block1a39.PORTAADDR7
address_a[7] => ram_block1a40.PORTAADDR7
address_a[7] => ram_block1a41.PORTAADDR7
address_a[7] => ram_block1a42.PORTAADDR7
address_a[7] => ram_block1a43.PORTAADDR7
address_a[7] => ram_block1a44.PORTAADDR7
address_a[7] => ram_block1a45.PORTAADDR7
address_a[7] => ram_block1a46.PORTAADDR7
address_a[7] => ram_block1a47.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[8] => ram_block1a12.PORTAADDR8
address_a[8] => ram_block1a13.PORTAADDR8
address_a[8] => ram_block1a14.PORTAADDR8
address_a[8] => ram_block1a15.PORTAADDR8
address_a[8] => ram_block1a16.PORTAADDR8
address_a[8] => ram_block1a17.PORTAADDR8
address_a[8] => ram_block1a18.PORTAADDR8
address_a[8] => ram_block1a19.PORTAADDR8
address_a[8] => ram_block1a20.PORTAADDR8
address_a[8] => ram_block1a21.PORTAADDR8
address_a[8] => ram_block1a22.PORTAADDR8
address_a[8] => ram_block1a23.PORTAADDR8
address_a[8] => ram_block1a24.PORTAADDR8
address_a[8] => ram_block1a25.PORTAADDR8
address_a[8] => ram_block1a26.PORTAADDR8
address_a[8] => ram_block1a27.PORTAADDR8
address_a[8] => ram_block1a28.PORTAADDR8
address_a[8] => ram_block1a29.PORTAADDR8
address_a[8] => ram_block1a30.PORTAADDR8
address_a[8] => ram_block1a31.PORTAADDR8
address_a[8] => ram_block1a32.PORTAADDR8
address_a[8] => ram_block1a33.PORTAADDR8
address_a[8] => ram_block1a34.PORTAADDR8
address_a[8] => ram_block1a35.PORTAADDR8
address_a[8] => ram_block1a36.PORTAADDR8
address_a[8] => ram_block1a37.PORTAADDR8
address_a[8] => ram_block1a38.PORTAADDR8
address_a[8] => ram_block1a39.PORTAADDR8
address_a[8] => ram_block1a40.PORTAADDR8
address_a[8] => ram_block1a41.PORTAADDR8
address_a[8] => ram_block1a42.PORTAADDR8
address_a[8] => ram_block1a43.PORTAADDR8
address_a[8] => ram_block1a44.PORTAADDR8
address_a[8] => ram_block1a45.PORTAADDR8
address_a[8] => ram_block1a46.PORTAADDR8
address_a[8] => ram_block1a47.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
address_a[9] => ram_block1a10.PORTAADDR9
address_a[9] => ram_block1a11.PORTAADDR9
address_a[9] => ram_block1a12.PORTAADDR9
address_a[9] => ram_block1a13.PORTAADDR9
address_a[9] => ram_block1a14.PORTAADDR9
address_a[9] => ram_block1a15.PORTAADDR9
address_a[9] => ram_block1a16.PORTAADDR9
address_a[9] => ram_block1a17.PORTAADDR9
address_a[9] => ram_block1a18.PORTAADDR9
address_a[9] => ram_block1a19.PORTAADDR9
address_a[9] => ram_block1a20.PORTAADDR9
address_a[9] => ram_block1a21.PORTAADDR9
address_a[9] => ram_block1a22.PORTAADDR9
address_a[9] => ram_block1a23.PORTAADDR9
address_a[9] => ram_block1a24.PORTAADDR9
address_a[9] => ram_block1a25.PORTAADDR9
address_a[9] => ram_block1a26.PORTAADDR9
address_a[9] => ram_block1a27.PORTAADDR9
address_a[9] => ram_block1a28.PORTAADDR9
address_a[9] => ram_block1a29.PORTAADDR9
address_a[9] => ram_block1a30.PORTAADDR9
address_a[9] => ram_block1a31.PORTAADDR9
address_a[9] => ram_block1a32.PORTAADDR9
address_a[9] => ram_block1a33.PORTAADDR9
address_a[9] => ram_block1a34.PORTAADDR9
address_a[9] => ram_block1a35.PORTAADDR9
address_a[9] => ram_block1a36.PORTAADDR9
address_a[9] => ram_block1a37.PORTAADDR9
address_a[9] => ram_block1a38.PORTAADDR9
address_a[9] => ram_block1a39.PORTAADDR9
address_a[9] => ram_block1a40.PORTAADDR9
address_a[9] => ram_block1a41.PORTAADDR9
address_a[9] => ram_block1a42.PORTAADDR9
address_a[9] => ram_block1a43.PORTAADDR9
address_a[9] => ram_block1a44.PORTAADDR9
address_a[9] => ram_block1a45.PORTAADDR9
address_a[9] => ram_block1a46.PORTAADDR9
address_a[9] => ram_block1a47.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[10] => ram_block1a4.PORTAADDR10
address_a[10] => ram_block1a5.PORTAADDR10
address_a[10] => ram_block1a6.PORTAADDR10
address_a[10] => ram_block1a7.PORTAADDR10
address_a[10] => ram_block1a8.PORTAADDR10
address_a[10] => ram_block1a9.PORTAADDR10
address_a[10] => ram_block1a10.PORTAADDR10
address_a[10] => ram_block1a11.PORTAADDR10
address_a[10] => ram_block1a12.PORTAADDR10
address_a[10] => ram_block1a13.PORTAADDR10
address_a[10] => ram_block1a14.PORTAADDR10
address_a[10] => ram_block1a15.PORTAADDR10
address_a[10] => ram_block1a16.PORTAADDR10
address_a[10] => ram_block1a17.PORTAADDR10
address_a[10] => ram_block1a18.PORTAADDR10
address_a[10] => ram_block1a19.PORTAADDR10
address_a[10] => ram_block1a20.PORTAADDR10
address_a[10] => ram_block1a21.PORTAADDR10
address_a[10] => ram_block1a22.PORTAADDR10
address_a[10] => ram_block1a23.PORTAADDR10
address_a[10] => ram_block1a24.PORTAADDR10
address_a[10] => ram_block1a25.PORTAADDR10
address_a[10] => ram_block1a26.PORTAADDR10
address_a[10] => ram_block1a27.PORTAADDR10
address_a[10] => ram_block1a28.PORTAADDR10
address_a[10] => ram_block1a29.PORTAADDR10
address_a[10] => ram_block1a30.PORTAADDR10
address_a[10] => ram_block1a31.PORTAADDR10
address_a[10] => ram_block1a32.PORTAADDR10
address_a[10] => ram_block1a33.PORTAADDR10
address_a[10] => ram_block1a34.PORTAADDR10
address_a[10] => ram_block1a35.PORTAADDR10
address_a[10] => ram_block1a36.PORTAADDR10
address_a[10] => ram_block1a37.PORTAADDR10
address_a[10] => ram_block1a38.PORTAADDR10
address_a[10] => ram_block1a39.PORTAADDR10
address_a[10] => ram_block1a40.PORTAADDR10
address_a[10] => ram_block1a41.PORTAADDR10
address_a[10] => ram_block1a42.PORTAADDR10
address_a[10] => ram_block1a43.PORTAADDR10
address_a[10] => ram_block1a44.PORTAADDR10
address_a[10] => ram_block1a45.PORTAADDR10
address_a[10] => ram_block1a46.PORTAADDR10
address_a[10] => ram_block1a47.PORTAADDR10
address_a[11] => ram_block1a0.PORTAADDR11
address_a[11] => ram_block1a1.PORTAADDR11
address_a[11] => ram_block1a2.PORTAADDR11
address_a[11] => ram_block1a3.PORTAADDR11
address_a[11] => ram_block1a4.PORTAADDR11
address_a[11] => ram_block1a5.PORTAADDR11
address_a[11] => ram_block1a6.PORTAADDR11
address_a[11] => ram_block1a7.PORTAADDR11
address_a[11] => ram_block1a8.PORTAADDR11
address_a[11] => ram_block1a9.PORTAADDR11
address_a[11] => ram_block1a10.PORTAADDR11
address_a[11] => ram_block1a11.PORTAADDR11
address_a[11] => ram_block1a12.PORTAADDR11
address_a[11] => ram_block1a13.PORTAADDR11
address_a[11] => ram_block1a14.PORTAADDR11
address_a[11] => ram_block1a15.PORTAADDR11
address_a[11] => ram_block1a16.PORTAADDR11
address_a[11] => ram_block1a17.PORTAADDR11
address_a[11] => ram_block1a18.PORTAADDR11
address_a[11] => ram_block1a19.PORTAADDR11
address_a[11] => ram_block1a20.PORTAADDR11
address_a[11] => ram_block1a21.PORTAADDR11
address_a[11] => ram_block1a22.PORTAADDR11
address_a[11] => ram_block1a23.PORTAADDR11
address_a[11] => ram_block1a24.PORTAADDR11
address_a[11] => ram_block1a25.PORTAADDR11
address_a[11] => ram_block1a26.PORTAADDR11
address_a[11] => ram_block1a27.PORTAADDR11
address_a[11] => ram_block1a28.PORTAADDR11
address_a[11] => ram_block1a29.PORTAADDR11
address_a[11] => ram_block1a30.PORTAADDR11
address_a[11] => ram_block1a31.PORTAADDR11
address_a[11] => ram_block1a32.PORTAADDR11
address_a[11] => ram_block1a33.PORTAADDR11
address_a[11] => ram_block1a34.PORTAADDR11
address_a[11] => ram_block1a35.PORTAADDR11
address_a[11] => ram_block1a36.PORTAADDR11
address_a[11] => ram_block1a37.PORTAADDR11
address_a[11] => ram_block1a38.PORTAADDR11
address_a[11] => ram_block1a39.PORTAADDR11
address_a[11] => ram_block1a40.PORTAADDR11
address_a[11] => ram_block1a41.PORTAADDR11
address_a[11] => ram_block1a42.PORTAADDR11
address_a[11] => ram_block1a43.PORTAADDR11
address_a[11] => ram_block1a44.PORTAADDR11
address_a[11] => ram_block1a45.PORTAADDR11
address_a[11] => ram_block1a46.PORTAADDR11
address_a[11] => ram_block1a47.PORTAADDR11
address_a[12] => address_reg_a[0].DATAIN
address_a[12] => decode_4oa:deep_decode.data[0]
address_a[13] => address_reg_a[1].DATAIN
address_a[13] => decode_4oa:deep_decode.data[1]
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
clock0 => ram_block1a18.CLK0
clock0 => ram_block1a19.CLK0
clock0 => ram_block1a20.CLK0
clock0 => ram_block1a21.CLK0
clock0 => ram_block1a22.CLK0
clock0 => ram_block1a23.CLK0
clock0 => ram_block1a24.CLK0
clock0 => ram_block1a25.CLK0
clock0 => ram_block1a26.CLK0
clock0 => ram_block1a27.CLK0
clock0 => ram_block1a28.CLK0
clock0 => ram_block1a29.CLK0
clock0 => ram_block1a30.CLK0
clock0 => ram_block1a31.CLK0
clock0 => ram_block1a32.CLK0
clock0 => ram_block1a33.CLK0
clock0 => ram_block1a34.CLK0
clock0 => ram_block1a35.CLK0
clock0 => ram_block1a36.CLK0
clock0 => ram_block1a37.CLK0
clock0 => ram_block1a38.CLK0
clock0 => ram_block1a39.CLK0
clock0 => ram_block1a40.CLK0
clock0 => ram_block1a41.CLK0
clock0 => ram_block1a42.CLK0
clock0 => ram_block1a43.CLK0
clock0 => ram_block1a44.CLK0
clock0 => ram_block1a45.CLK0
clock0 => ram_block1a46.CLK0
clock0 => ram_block1a47.CLK0
clock0 => address_reg_a[1].CLK
clock0 => address_reg_a[0].CLK
clock0 => out_address_reg_a[1].CLK
clock0 => out_address_reg_a[0].CLK
q_a[0] <= mux_vjb:mux2.result[0]
q_a[1] <= mux_vjb:mux2.result[1]
q_a[2] <= mux_vjb:mux2.result[2]
q_a[3] <= mux_vjb:mux2.result[3]
q_a[4] <= mux_vjb:mux2.result[4]
q_a[5] <= mux_vjb:mux2.result[5]
q_a[6] <= mux_vjb:mux2.result[6]
q_a[7] <= mux_vjb:mux2.result[7]
q_a[8] <= mux_vjb:mux2.result[8]
q_a[9] <= mux_vjb:mux2.result[9]
q_a[10] <= mux_vjb:mux2.result[10]
q_a[11] <= mux_vjb:mux2.result[11]


|dds_new|sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|decode_4oa:deep_decode
data[0] => w_anode218w[1].IN1
data[0] => w_anode234w[1].IN1
data[1] => w_anode226w[2].IN1
data[1] => w_anode234w[2].IN1
enable => w_anode205w[1].IN0
enable => w_anode218w[1].IN0
enable => w_anode226w[1].IN0
enable => w_anode234w[1].IN0
eq[0] <= w_anode205w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= w_anode218w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[2] <= w_anode226w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[3] <= w_anode234w[2].DB_MAX_OUTPUT_PORT_TYPE


|dds_new|sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|mux_vjb:mux2
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= result_node[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= result_node[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= result_node[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= result_node[11].DB_MAX_OUTPUT_PORT_TYPE