dds_new.hier_info

来自「驱动时钟加入了PLL,使得DDS的驱动时钟可变.32位的NCO使得DDS的分辨率」· HIER_INFO 代码 · 共 1,590 行 · 第 1/4 页

clk[4] <= <GND>
clk[5] <= <GND>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>


|dds_new|sinrom:inst3
address[0] => address[0]~13.IN1
address[1] => address[1]~12.IN1
address[2] => address[2]~11.IN1
address[3] => address[3]~10.IN1
address[4] => address[4]~9.IN1
address[5] => address[5]~8.IN1
address[6] => address[6]~7.IN1
address[7] => address[7]~6.IN1
address[8] => address[8]~5.IN1
address[9] => address[9]~4.IN1
address[10] => address[10]~3.IN1
address[11] => address[11]~2.IN1
address[12] => address[12]~1.IN1
address[13] => address[13]~0.IN1
clock => clock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a
q[8] <= altsyncram:altsyncram_component.q_a
q[9] <= altsyncram:altsyncram_component.q_a
q[10] <= altsyncram:altsyncram_component.q_a
q[11] <= altsyncram:altsyncram_component.q_a


|dds_new|sinrom:inst3|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_5071:auto_generated.address_a[0]
address_a[1] => altsyncram_5071:auto_generated.address_a[1]
address_a[2] => altsyncram_5071:auto_generated.address_a[2]
address_a[3] => altsyncram_5071:auto_generated.address_a[3]
address_a[4] => altsyncram_5071:auto_generated.address_a[4]
address_a[5] => altsyncram_5071:auto_generated.address_a[5]
address_a[6] => altsyncram_5071:auto_generated.address_a[6]
address_a[7] => altsyncram_5071:auto_generated.address_a[7]
address_a[8] => altsyncram_5071:auto_generated.address_a[8]
address_a[9] => altsyncram_5071:auto_generated.address_a[9]
address_a[10] => altsyncram_5071:auto_generated.address_a[10]
address_a[11] => altsyncram_5071:auto_generated.address_a[11]
address_a[12] => altsyncram_5071:auto_generated.address_a[12]
address_a[13] => altsyncram_5071:auto_generated.address_a[13]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_5071:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_5071:auto_generated.q_a[0]
q_a[1] <= altsyncram_5071:auto_generated.q_a[1]
q_a[2] <= altsyncram_5071:auto_generated.q_a[2]
q_a[3] <= altsyncram_5071:auto_generated.q_a[3]
q_a[4] <= altsyncram_5071:auto_generated.q_a[4]
q_a[5] <= altsyncram_5071:auto_generated.q_a[5]
q_a[6] <= altsyncram_5071:auto_generated.q_a[6]
q_a[7] <= altsyncram_5071:auto_generated.q_a[7]
q_a[8] <= altsyncram_5071:auto_generated.q_a[8]
q_a[9] <= altsyncram_5071:auto_generated.q_a[9]
q_a[10] <= altsyncram_5071:auto_generated.q_a[10]
q_a[11] <= altsyncram_5071:auto_generated.q_a[11]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|dds_new|sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[0] => ram_block1a24.PORTAADDR
address_a[0] => ram_block1a25.PORTAADDR
address_a[0] => ram_block1a26.PORTAADDR
address_a[0] => ram_block1a27.PORTAADDR
address_a[0] => ram_block1a28.PORTAADDR
address_a[0] => ram_block1a29.PORTAADDR
address_a[0] => ram_block1a30.PORTAADDR
address_a[0] => ram_block1a31.PORTAADDR
address_a[0] => ram_block1a32.PORTAADDR
address_a[0] => ram_block1a33.PORTAADDR
address_a[0] => ram_block1a34.PORTAADDR
address_a[0] => ram_block1a35.PORTAADDR
address_a[0] => ram_block1a36.PORTAADDR
address_a[0] => ram_block1a37.PORTAADDR
address_a[0] => ram_block1a38.PORTAADDR
address_a[0] => ram_block1a39.PORTAADDR
address_a[0] => ram_block1a40.PORTAADDR
address_a[0] => ram_block1a41.PORTAADDR
address_a[0] => ram_block1a42.PORTAADDR
address_a[0] => ram_block1a43.PORTAADDR
address_a[0] => ram_block1a44.PORTAADDR
address_a[0] => ram_block1a45.PORTAADDR
address_a[0] => ram_block1a46.PORTAADDR
address_a[0] => ram_block1a47.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[1] => ram_block1a18.PORTAADDR1
address_a[1] => ram_block1a19.PORTAADDR1
address_a[1] => ram_block1a20.PORTAADDR1
address_a[1] => ram_block1a21.PORTAADDR1
address_a[1] => ram_block1a22.PORTAADDR1
address_a[1] => ram_block1a23.PORTAADDR1
address_a[1] => ram_block1a24.PORTAADDR1
address_a[1] => ram_block1a25.PORTAADDR1
address_a[1] => ram_block1a26.PORTAADDR1
address_a[1] => ram_block1a27.PORTAADDR1
address_a[1] => ram_block1a28.PORTAADDR1
address_a[1] => ram_block1a29.PORTAADDR1
address_a[1] => ram_block1a30.PORTAADDR1
address_a[1] => ram_block1a31.PORTAADDR1
address_a[1] => ram_block1a32.PORTAADDR1
address_a[1] => ram_block1a33.PORTAADDR1
address_a[1] => ram_block1a34.PORTAADDR1
address_a[1] => ram_block1a35.PORTAADDR1
address_a[1] => ram_block1a36.PORTAADDR1
address_a[1] => ram_block1a37.PORTAADDR1
address_a[1] => ram_block1a38.PORTAADDR1
address_a[1] => ram_block1a39.PORTAADDR1
address_a[1] => ram_block1a40.PORTAADDR1
address_a[1] => ram_block1a41.PORTAADDR1
address_a[1] => ram_block1a42.PORTAADDR1
address_a[1] => ram_block1a43.PORTAADDR1
address_a[1] => ram_block1a44.PORTAADDR1
address_a[1] => ram_block1a45.PORTAADDR1
address_a[1] => ram_block1a46.PORTAADDR1
address_a[1] => ram_block1a47.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[2] => ram_block1a16.PORTAADDR2
address_a[2] => ram_block1a17.PORTAADDR2
address_a[2] => ram_block1a18.PORTAADDR2
address_a[2] => ram_block1a19.PORTAADDR2
address_a[2] => ram_block1a20.PORTAADDR2
address_a[2] => ram_block1a21.PORTAADDR2
address_a[2] => ram_block1a22.PORTAADDR2
address_a[2] => ram_block1a23.PORTAADDR2
address_a[2] => ram_block1a24.PORTAADDR2
address_a[2] => ram_block1a25.PORTAADDR2
address_a[2] => ram_block1a26.PORTAADDR2
address_a[2] => ram_block1a27.PORTAADDR2
address_a[2] => ram_block1a28.PORTAADDR2
address_a[2] => ram_block1a29.PORTAADDR2
address_a[2] => ram_block1a30.PORTAADDR2
address_a[2] => ram_block1a31.PORTAADDR2
address_a[2] => ram_block1a32.PORTAADDR2
address_a[2] => ram_block1a33.PORTAADDR2
address_a[2] => ram_block1a34.PORTAADDR2
address_a[2] => ram_block1a35.PORTAADDR2
address_a[2] => ram_block1a36.PORTAADDR2
address_a[2] => ram_block1a37.PORTAADDR2
address_a[2] => ram_block1a38.PORTAADDR2
address_a[2] => ram_block1a39.PORTAADDR2
address_a[2] => ram_block1a40.PORTAADDR2
address_a[2] => ram_block1a41.PORTAADDR2
address_a[2] => ram_block1a42.PORTAADDR2
address_a[2] => ram_block1a43.PORTAADDR2
address_a[2] => ram_block1a44.PORTAADDR2
address_a[2] => ram_block1a45.PORTAADDR2
address_a[2] => ram_block1a46.PORTAADDR2
address_a[2] => ram_block1a47.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[3] => ram_block1a16.PORTAADDR3
address_a[3] => ram_block1a17.PORTAADDR3
address_a[3] => ram_block1a18.PORTAADDR3
address_a[3] => ram_block1a19.PORTAADDR3
address_a[3] => ram_block1a20.PORTAADDR3
address_a[3] => ram_block1a21.PORTAADDR3
address_a[3] => ram_block1a22.PORTAADDR3
address_a[3] => ram_block1a23.PORTAADDR3
address_a[3] => ram_block1a24.PORTAADDR3
address_a[3] => ram_block1a25.PORTAADDR3
address_a[3] => ram_block1a26.PORTAADDR3
address_a[3] => ram_block1a27.PORTAADDR3
address_a[3] => ram_block1a28.PORTAADDR3
address_a[3] => ram_block1a29.PORTAADDR3
address_a[3] => ram_block1a30.PORTAADDR3
address_a[3] => ram_block1a31.PORTAADDR3
address_a[3] => ram_block1a32.PORTAADDR3
address_a[3] => ram_block1a33.PORTAADDR3
address_a[3] => ram_block1a34.PORTAADDR3
address_a[3] => ram_block1a35.PORTAADDR3
address_a[3] => ram_block1a36.PORTAADDR3
address_a[3] => ram_block1a37.PORTAADDR3
address_a[3] => ram_block1a38.PORTAADDR3
address_a[3] => ram_block1a39.PORTAADDR3
address_a[3] => ram_block1a40.PORTAADDR3
address_a[3] => ram_block1a41.PORTAADDR3
address_a[3] => ram_block1a42.PORTAADDR3
address_a[3] => ram_block1a43.PORTAADDR3
address_a[3] => ram_block1a44.PORTAADDR3
address_a[3] => ram_block1a45.PORTAADDR3
address_a[3] => ram_block1a46.PORTAADDR3
address_a[3] => ram_block1a47.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[4] => ram_block1a16.PORTAADDR4
address_a[4] => ram_block1a17.PORTAADDR4
address_a[4] => ram_block1a18.PORTAADDR4
address_a[4] => ram_block1a19.PORTAADDR4
address_a[4] => ram_block1a20.PORTAADDR4
address_a[4] => ram_block1a21.PORTAADDR4
address_a[4] => ram_block1a22.PORTAADDR4
address_a[4] => ram_block1a23.PORTAADDR4
address_a[4] => ram_block1a24.PORTAADDR4
address_a[4] => ram_block1a25.PORTAADDR4
address_a[4] => ram_block1a26.PORTAADDR4
address_a[4] => ram_block1a27.PORTAADDR4
address_a[4] => ram_block1a28.PORTAADDR4
address_a[4] => ram_block1a29.PORTAADDR4
address_a[4] => ram_block1a30.PORTAADDR4
address_a[4] => ram_block1a31.PORTAADDR4
address_a[4] => ram_block1a32.PORTAADDR4
address_a[4] => ram_block1a33.PORTAADDR4
address_a[4] => ram_block1a34.PORTAADDR4
address_a[4] => ram_block1a35.PORTAADDR4
address_a[4] => ram_block1a36.PORTAADDR4
address_a[4] => ram_block1a37.PORTAADDR4
address_a[4] => ram_block1a38.PORTAADDR4
address_a[4] => ram_block1a39.PORTAADDR4
address_a[4] => ram_block1a40.PORTAADDR4
address_a[4] => ram_block1a41.PORTAADDR4
address_a[4] => ram_block1a42.PORTAADDR4
address_a[4] => ram_block1a43.PORTAADDR4
address_a[4] => ram_block1a44.PORTAADDR4
address_a[4] => ram_block1a45.PORTAADDR4
address_a[4] => ram_block1a46.PORTAADDR4
address_a[4] => ram_block1a47.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[5] => ram_block1a16.PORTAADDR5
address_a[5] => ram_block1a17.PORTAADDR5
address_a[5] => ram_block1a18.PORTAADDR5
address_a[5] => ram_block1a19.PORTAADDR5
address_a[5] => ram_block1a20.PORTAADDR5
address_a[5] => ram_block1a21.PORTAADDR5
address_a[5] => ram_block1a22.PORTAADDR5
address_a[5] => ram_block1a23.PORTAADDR5
address_a[5] => ram_block1a24.PORTAADDR5
address_a[5] => ram_block1a25.PORTAADDR5
address_a[5] => ram_block1a26.PORTAADDR5
address_a[5] => ram_block1a27.PORTAADDR5
address_a[5] => ram_block1a28.PORTAADDR5
address_a[5] => ram_block1a29.PORTAADDR5
address_a[5] => ram_block1a30.PORTAADDR5
address_a[5] => ram_block1a31.PORTAADDR5
address_a[5] => ram_block1a32.PORTAADDR5
address_a[5] => ram_block1a33.PORTAADDR5
address_a[5] => ram_block1a34.PORTAADDR5
address_a[5] => ram_block1a35.PORTAADDR5
address_a[5] => ram_block1a36.PORTAADDR5
address_a[5] => ram_block1a37.PORTAADDR5
address_a[5] => ram_block1a38.PORTAADDR5
address_a[5] => ram_block1a39.PORTAADDR5
address_a[5] => ram_block1a40.PORTAADDR5