dds_new.tan.rpt

驱动时钟加入了PLL,使得DDS的驱动时钟可变.32位的NCO使得DDS的分辨率可以做到Hz量级

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                           ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                          ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; pll4:inst4|altpll:altpll_component|_clk0 ;                    ; PLL output ; 120.0 MHz        ; 0.000 ns      ; 0.000 ns     ; clk      ; 6                     ; 1                   ; -2.358 ns ;              ;
; clk                                      ;                    ; User Pin   ; 20.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'pll4:inst4|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                   ; To                                                                                                            ; From Clock                               ; To Clock                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 0.896 ns                                ; 134.46 MHz ( period = 7.437 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a6~porta_address_reg11  ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.119 ns                  ; 7.223 ns                ;
; 0.896 ns                                ; 134.46 MHz ( period = 7.437 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a6~porta_address_reg10  ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.119 ns                  ; 7.223 ns                ;
; 0.896 ns                                ; 134.46 MHz ( period = 7.437 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a6~porta_address_reg9   ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.119 ns                  ; 7.223 ns                ;
; 0.896 ns                                ; 134.46 MHz ( period = 7.437 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a6~porta_address_reg8   ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.119 ns                  ; 7.223 ns                ;
; 0.896 ns                                ; 134.46 MHz ( period = 7.437 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a6~porta_address_reg7   ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.119 ns                  ; 7.223 ns                ;
; 0.896 ns                                ; 134.46 MHz ( period = 7.437 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a6~porta_address_reg6   ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.119 ns                  ; 7.223 ns                ;
; 0.896 ns                                ; 134.46 MHz ( period = 7.437 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a6~porta_address_reg5   ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.119 ns                  ; 7.223 ns                ;
; 0.896 ns                                ; 134.46 MHz ( period = 7.437 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a6~porta_address_reg4   ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.119 ns                  ; 7.223 ns                ;
; 0.896 ns                                ; 134.46 MHz ( period = 7.437 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a6~porta_address_reg3   ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.119 ns                  ; 7.223 ns                ;
; 0.896 ns                                ; 134.46 MHz ( period = 7.437 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a6~porta_address_reg2   ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.119 ns                  ; 7.223 ns                ;
; 0.896 ns                                ; 134.46 MHz ( period = 7.437 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a6~porta_address_reg1   ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.119 ns                  ; 7.223 ns                ;
; 0.896 ns                                ; 134.46 MHz ( period = 7.437 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a6~porta_address_reg0   ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.119 ns                  ; 7.223 ns                ;
; 0.906 ns                                ; 134.64 MHz ( period = 7.427 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a4~porta_address_reg11  ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.115 ns                  ; 7.209 ns                ;
; 0.906 ns                                ; 134.64 MHz ( period = 7.427 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a4~porta_address_reg10  ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.115 ns                  ; 7.209 ns                ;
; 0.906 ns                                ; 134.64 MHz ( period = 7.427 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a4~porta_address_reg9   ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.115 ns                  ; 7.209 ns                ;
; 0.906 ns                                ; 134.64 MHz ( period = 7.427 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a4~porta_address_reg8   ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.115 ns                  ; 7.209 ns                ;
; 0.906 ns                                ; 134.64 MHz ( period = 7.427 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a4~porta_address_reg7   ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.115 ns                  ; 7.209 ns                ;
; 0.906 ns                                ; 134.64 MHz ( period = 7.427 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a4~porta_address_reg6   ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.115 ns                  ; 7.209 ns                ;
; 0.906 ns                                ; 134.64 MHz ( period = 7.427 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a4~porta_address_reg5   ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.115 ns                  ; 7.209 ns                ;
; 0.906 ns                                ; 134.64 MHz ( period = 7.427 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a4~porta_address_reg4   ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.115 ns                  ; 7.209 ns                ;
; 0.906 ns                                ; 134.64 MHz ( period = 7.427 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a4~porta_address_reg3   ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.115 ns                  ; 7.209 ns                ;
; 0.906 ns                                ; 134.64 MHz ( period = 7.427 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a4~porta_address_reg2   ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.115 ns                  ; 7.209 ns                ;
; 0.906 ns                                ; 134.64 MHz ( period = 7.427 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a4~porta_address_reg1   ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.115 ns                  ; 7.209 ns                ;
; 0.906 ns                                ; 134.64 MHz ( period = 7.427 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a4~porta_address_reg0   ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.115 ns                  ; 7.209 ns                ;
; 0.912 ns                                ; 134.75 MHz ( period = 7.421 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a10~porta_address_reg11 ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.109 ns                  ; 7.197 ns                ;
; 0.912 ns                                ; 134.75 MHz ( period = 7.421 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a10~porta_address_reg10 ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.109 ns                  ; 7.197 ns                ;
; 0.912 ns                                ; 134.75 MHz ( period = 7.421 ns )                    ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0] ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a10~porta_address_reg9  ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 8.333 ns                    ; 8.109 ns                  ; 7.197 ns                ;