dds_new.tan.rpt

来自「驱动时钟加入了PLL,使得DDS的驱动时钟可变.32位的NCO使得DDS的分辨率」· RPT 代码 · 共 209 行 · 第 1/5 页

; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+---------------------------------------------------------+----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+
; Type                                                    ; Slack    ; Required Time                    ; Actual Time                      ; From                                                                                    ; To                                                                                                           ; From Clock                               ; To Clock                                 ; Failed Paths ;
+---------------------------------------------------------+----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+
; Worst-case tsu                                          ; N/A      ; None                             ; 12.826 ns                        ; phase[7]                                                                                ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a6~porta_address_reg11 ; --                                       ; clk                                      ; 0            ;
; Worst-case tco                                          ; N/A      ; None                             ; 9.452 ns                         ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0]  ; A[29]                                                                                                        ; clk                                      ; --                                       ; 0            ;
; Worst-case tpd                                          ; N/A      ; None                             ; 14.841 ns                        ; phase[7]                                                                                ; A[29]                                                                                                        ; --                                       ; --                                       ; 0            ;
; Worst-case th                                           ; N/A      ; None                             ; -3.554 ns                        ; phase[20]                                                                               ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a17~porta_address_reg2 ; --                                       ; clk                                      ; 0            ;
; Clock Setup: 'pll4:inst4|altpll:altpll_component|_clk0' ; 0.896 ns ; 120.00 MHz ( period = 8.333 ns ) ; 134.46 MHz ( period = 7.437 ns ) ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[0]  ; sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|ram_block1a6~porta_address_reg11 ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'pll4:inst4|altpll:altpll_component|_clk0'  ; 0.795 ns ; 120.00 MHz ( period = 8.333 ns ) ; N/A                              ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[16] ; acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[16]                      ; pll4:inst4|altpll:altpll_component|_clk0 ; pll4:inst4|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                            ;          ;                                  ;                                  ;                                                                                         ;                                                                                                              ;                                          ;                                          ; 0            ;
+---------------------------------------------------------+----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+