sine.map.rpt

原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成

; sld_ip_version        ; 1          ; Integer                                                                                                  ;
; sld_ip_minor_version  ; 2          ; Integer                                                                                                  ;
; sld_common_ip_version ; 0          ; Integer                                                                                                  ;
; width_word            ; 8          ; Untyped                                                                                                  ;
; numwords              ; 64         ; Untyped                                                                                                  ;
; widthad               ; 6          ; Untyped                                                                                                  ;
; shift_count_bits      ; 4          ; Untyped                                                                                                  ;
; cvalue                ; 00000000   ; Untyped                                                                                                  ;
; is_data_in_ram        ; 1          ; Untyped                                                                                                  ;
; is_readable           ; 1          ; Untyped                                                                                                  ;
; node_name             ; 1919905073 ; Untyped                                                                                                  ;
+-----------------------+------------+----------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst ;
+--------------------------+----------------------------------+---------+
; Parameter Name           ; Value                            ; Type    ;
+--------------------------+----------------------------------+---------+
; sld_hub_ip_version       ; 1                                ; Untyped ;
; sld_hub_ip_minor_version ; 2                                ; Untyped ;
; sld_common_ip_version    ; 0                                ; Untyped ;
; device_family            ; Cyclone II                       ; Untyped ;
; n_nodes                  ; 1                                ; Untyped ;
; n_sel_bits               ; 1                                ; Untyped ;
; n_node_ir_bits           ; 5                                ; Untyped ;
; node_info                ; 00001000000110000110111000000000 ; Binary  ;
+--------------------------+----------------------------------+---------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------+
; In-System Memory Content Editor Settings                                                                                           ;
+----------------+-------------+-------+-------+------------+------------------------------------------------------------------------+
; Instance Index ; Instance ID ; Width ; Depth ; Mode       ; Hierarchy Location                                                     ;
+----------------+-------------+-------+-------+------------+------------------------------------------------------------------------+
; 0              ; rom1        ; 8     ; 64    ; Read/Write ; rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated ;
+----------------+-------------+-------+-------+------------+------------------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/quartus/myproject/正弦信号发生器/sine.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Nov 11 23:03:06 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sine -c sine
Info: Found 2 design units, including 1 entities, in source file rom1.vhd
    Info: Found design unit 1: rom1-SYN
    Info: Found entity 1: rom1
Info: Found 2 design units, including 1 entities, in source file sine.vhd
    Info: Found design unit 1: sine-beh
    Info: Found entity 1: sine
Info: Elaborating entity "sine" for the top level hierarchy
Info: Elaborating entity "rom1" for hierarchy "rom1:u1"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "rom1:u1|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_4d51.tdf
    Info: Found entity 1: altsyncram_4d51
Info: Elaborating entity "altsyncram_4d51" for hierarchy "rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_b192.tdf
    Info: Found entity 1: altsyncram_b192
Info: Elaborating entity "altsyncram_b192" for hierarchy "rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|altsyncram_b192:altsyncram1"
Info: Found 3 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd
    Info: Found design unit 1: sld_mod_ram_rom_pack
    Info: Found design unit 2: sld_mod_ram_rom-rtl
    Info: Found entity 1: sld_mod_ram_rom
Info: Elaborating entity "sld_mod_ram_rom" for hierarchy "rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2"
Info: Found 2 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd
    Info: Found design unit 1: sld_rom_sr-INFO_REG
    Info: Found entity 1: sld_rom_sr
Info: Elaborating entity "sld_rom_sr" for hierarchy "rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr"
Info: Found 6 design units, including 2 entities, in source file c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd
    Info: Found design unit 1: HUB_PACK
    Info: Found design unit 2: JTAG_PACK
    Info: Found design unit 3: sld_hub-rtl
    Info: Found design unit 4: sld_jtag_state_machine-rtl
    Info: Found entity 1: sld_hub
    Info: Found entity 2: sld_jtag_state_machine
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_shiftreg.tdf
    Info: Found entity 1: lpm_shiftreg
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_decode.tdf
    Info: Found entity 1: lpm_decode
Info: Found 1 design units, including 1 entities, in source file db/decode_rpe.tdf
    Info: Found entity 1: decode_rpe
Info: Found 2 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd
    Info: Found design unit 1: sld_dffex-DFFEX
    Info: Found entity 1: sld_dffex
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 202 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 9 output pins
    Info: Implemented 180 logic cells
    Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Nov 11 23:03:41 2008
    Info: Elapsed time: 00:00:37